SU1624691A1 - Analog-digital converter - Google Patents

Abstract

This invention relates to a measurement technique. The invention improves accuracy. This is achieved by the fact that the analog-to-digital converter containing adder 1, register 3, digital-analog converter 2, converter 4 voltage - coding adder 5, generator 6 clock pulses, entered block 7 comparison of codes, counter 9, element And 8 , register 10. 2 Il.

Description

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with

 Yu

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oh oh

figure 1

The invention relates to measurement technology and can be used in information and measurement data processing systems.

The purpose of the invention is to improve the accuracy of the converter.

FIG. 1 shows a functional diagram of the device; in fig. 2 - timing charts of the device.

The analog-to-digital converter (FIG. 1) contains adder 1, digital-analog converter 2, register 3, voltage converter 4 — code, digital adder 5, generator 6 clock pulses, code comparison block 7, element 8 AND, counter 9, register 10.

FIG. 2 marked; 11 - the first input of the adder 7; 12, 13, 14 - voltages, respectively, at the first and second outputs of block 7 and counter 9.

The device works as follows.

The analog input value x is fed to the first input of adder 1, the output of which forms the difference Dx x - xi. If the previous values are mind 0, then xi O and Dx x, if yu m4 0, then xi O and Dx x - xi. The value Dx is converted to code Ayi by converter 4. If Ayi 0 is accurate to the conversion error, block 7 sets the counter 9 to O and prohibits the passage of clock pulses to its input. Code Doo | enters the digital adder 5, where it is summed with the contents of register 3, which stores the value of the code in the digital adder 5 at the previous encoding. This code is entered again into register 3 and fed to the inputs of the DAC 2. When in the process of converting Doug 0 to within the error of conversion, block 7 permits the passage of clock pulses through element 8I to the input of counter 9. Counter 9 counts the clock pulses before it is filled determined by its capacity, in which the readout code of the conversion code is output to the register 10. If before filling in counter 9, the code is Du | becomes non-zero, then block 7 will set the counter 9 to O and prohibit the passage of clock pulses to its input. The reading of the code will be prohibited and the conversion process will continue as described above. Block 7 compares the code with a zero code.

Consider the operation of the device in the presence of interference.

When Dx 0, therefore, DN 0, block 7 permits the passage of clock

pulses through the element 8I to the input of the counter 9, the counter 9 counts the clock pulses until it is filled and outputs to the register 10 a read enable signal

converter code. If before filling in counter 9, the code is Du | will become non-zero as a result of interference, then block 7 will set counter 9 to O and prohibit the passage of clock pulses to its

the input (Fig. 2a), the reading of the code from the device will be prohibited and the next converter will continue the converter process until the value Dx is equal to O. As soon as the code Dy | 0,

block 7 permits the passage of clock pulses to counter 9, which generates a code read pulse from register 10, if during filling of counter 9 the difference Dx 0 and accordingly the code Du | 0

The moment of occurrence of a disturbance pulse and, accordingly, a change in the magnitude of Dx does not affect the operation of the device, since block 7 checks that Du | 0 per conversion cycle

(Fig, 26),

The capacity of the counter 9 is selected based on the intensity possibilities of the appearance of impulse noise so that the random conversion error is not

exceeded the given.

Analog-to-digital converter has the following technical advantages over the prototype.

The accuracy of the proposed analog-to-digital converter increases as a result of the fact that the probability of a false equality between the sample and the input signal in the event of interference,

So, if in an analog-to-digital converter-prototype the probability of the occurrence of an erroneous result at the output is D, then the probability of the occurrence of the correct result is 1 - D.

as a result of majority processing

the results of encoding the converter according to the criterion of their equality, the probability of the occurrence of an erroneous result decreases to the value of Dt, where D | “D. Therefore,

The intensity of the appearance of the correct result rises sharply, since 1 - D «1 - D |.

Claims (1)

Analog-to-digital converter containing an adder, a digital-to-analog converter, a voltage converter — a code, a digital adder, a clock generator, the first input of the adder is an input bus, a second input connected to the output of a digital-analog converter; the output of the adder is connected to the first input of the voltage converter — the code whose second input is connected to the output of the clock generator and the input of the digital adder; with the first group of outputs of the first register, the second group of outputs of which is connected to the inputs of the digital-to-analog converter, and the inputs of the first register are connected to the outputs of digital of adder otlmchayuschiy- in that, in order to increase the accuracy of 0 the converter, the second register is entered into it, the code comparison block, the And element, the counter, the voltage converter outputs — the code is connected to the corresponding inputs of the code comparison block, the first output of which is connected to the first input of the counter, and the second output to the first input of the AND element , the second input of which is connected to the output of the clock generator, and the output is connected to the second input of the counter, the output of which is connected to the input of the second register, the group of inputs of which is connected to the second group of outputs of the first register, and you The second register moves are the output bus.