SU1589308A1 - Device for presentation of information on television indicator screen - Google Patents

Abstract

The invention relates to automation and computing and can be used in devices for outputting alphanumeric information to a television display screen. The aim of the invention is to improve the speed of the device. The device contains the first 1 and second 2 blocks of RAM, the first register 3, multiplexer 4, block 5 of the permanent memory, shaper 6 raster line, block 7 of forming the video signal, television indicator 8, block 9 of control, first 10, second 11 and the third 12 blocks of AND elements, a block of 13 OR elements, the second 14 register, a block of 15 modulo-15 adders, a third register 16, the first 17 and a second 18 OR elements with corresponding connections. The speed of the device is increased by eliminating the need to transfer large amounts of information when modifying a small portion of the image and allowing the information to be displayed in parallel with its transfer to the first RAM block 1. 2 Il.

Description

The invention relates to automation and computer technology and can be used in devices for outputting alphanumeric information on screen 5 of a television indicator.

The purpose of the invention is to increase the speed of the device,

Pa fig. 1 shows a structural diagram of a device; Fig. 2 is a structural diagram of a control unit.

The device contains the first 1 and second 2 blocks of RAM, Norwegian register 3, multiplexer 4, (5l ok 5 permanent memory, forming 15 fel used raster lines, block 7 for generating a video signal, television indicator 8, control unit 9, first 10, second 11 and third 12 blocks of AND elements, block 13 of elements 20 jinn, second register 14, block 15 sumators modulo two * third register 16, first 17 and second 18 elements OR, information input-output 19, first 20 and second 21 control 25 Inputs, outputs 22-33 of the control unit from the first to the twelfth, input 34 select p hedgehog control unit ,, third 35 and fourth 36 control inputs.

The control unit 9 includes a 30 generator 37 synchronization pulses, a counter 38 of the number of elements of decomposition of symbols in the X coordinate, a counter JJ9 of the number of characters in the lines of the displayed symbol information, a counter 35 40 of the number of elements of decomposition of the symbols in the coordinate U, counter 41 of the number of lines symbolic information displayed, decoder 42, read-only memory (ROM) dd control microcommands and outputs 44-78.

Positions 79 and 80 indicate the address ¹ and 5 of the control inputs of the device. 45

During operation of the control unit 9, the synchronization pulse generator 37 generates pulses, synchronizing the <- day of the operation of the entire device. From its output, its pulses are fed to the inputs of block 7 (output 72) and counter 38. Transfer pulses from the second output of counter 38 go to the first input. counter 39 Transfer pulses from the second output of the counter 40 are fed to the $$ counter input. 41.

Codes. Status of the device from the first! . the outputs of counter_38 and 40 (outputs 73 hJ? 6), the second outputs of counters 39 and (outputs 75 and 78) and the output of register 14 (input 34) are fed to the inputs of the decoder 42 connected to the ROM 43. Using the ROM 43, in which microcommand codes, Write, Read, and Reset signals are generated (outputs 44-58, 63, 70, and 71) of all the main units of the device, lowercase (output 50) and frame (output 59) synchronizing pulses, signals for reading reverse beam codes in rows ( output 61) and frames (output 60), pulses Readiness for code reception (output 64), transfer pulses arriving at counter 40 from the counter and 39 (yield, 65), the block counter 9 reset pulses (66) output from the ROM 43 additionally vschayutsya dyer's weed control pulses 10, second 11 and third 12 units of AND gates (yields 67-69).

Counters 39 and 41 form the addresses of the first memory unit 1 (symbol code memory) - outputs 74 and 77, counters 40 and 41 - the addresses of the second memory unit 2 (raster memory) - outputs 76 and 77. Additionally, the addresses generated by the counters 39 and 40, are used to control blocks 5 and 6, which are a symbol generator (outputs 74 and 76),

Block 9 implements four main modes of operation of the device and an additional mode - information exchange when the data bus is off.

The mode number that is currently being implemented is recorded from input 35 to register 14. The register 14 is reset from input 36 of the device each time a new operating mode is switched. Before starting work, a general discharge of the registers is carried out.

The device operates as follows.

Character codes through input 19 are fed to the combined input-output of register 3 and input-output of the first memory unit 1. Here they are recorded in sequentially arranged cells in the order of entry 19.

The capacity of the first memory unit 1 is sufficient to store information about the full image displayed on the CRT screen, the capacity of register 3 is sufficient to store information about one line of text and the converted character codes. Register 3 is made in the form of a line of registers with independent

1589.308 management. According to the signals from the outputs of the control unit 9 in the raster formation mode, the codes are selected from register 3 and passed alternately to the symbol generator (blocks 5 and 6).

From the outputs of the block 5 of constant memory codes corresponding to the lines of the raster of the television decomposition of the symbol. catch, arrive at the shaper 6 raster-10 straight line and through it, the third block of 12 elements And, register 3, block 15 adders modulo two in the second block 2 of the memory. At this moment, the third register 16 is reset and the information from the output 15 of block 3 to block 2 passes unchanged.

In the raster regeneration mode, information words with a length of Ksh bits through register 3, the first block of 10 AND elements and block 13 of the OR elements come from block 2 to block 7 of the formation of the video signal, where K is the number of characters in the line; η is the length of the line video code of one character,

At this time, the second block of 11 elements And the signal from the output of block 9 is closed. In block 8, the image is reproduced on a CRT screen. Using blocks 11 and 12 of AND elements and block 13 of OR elements, the device implements the fourth mode of operation.

In this mode, using the third block of 12 AND elements, the connection between the output of the symbol generator from register 3 and further to the memory unit 2 is broken. Using the block 11 of the AND elements and the block 13 of the OR elements, a direct connection of the symbol generator with the block 7 is established to display the variable component of the images.

Due to this, with the simultaneous implementation of the third and fourth modes (if necessary), it is possible to combine the constant and variable components of the image. In block 1, a copy of the information displayed on the indicator screen is accumulated. After the accumulation of each next line of text, the corresponding bits of register 3 are reset by pulses from the outputs of block 9 (outputs 49 and 51), Pulses c. outputs 49 and 51 allow you to reset the register partially or completely. Partial reset allows you to save part 55 of the image of the variable component of the line of text, if it is repeated in adjacent lines. When recording information in register 3, signals from outputs 50 and 52 are used, which allow the weight of the recording to be in full or in part. The place of recording in register 3 is determined by the address formed in block 9 by counter 39 (output 74).

The recording location in block 1 is determined by the addresses formed by the counters 39 and 41 (outputs 74 and 77).

Addresses from the counters enter block 1 through the first input of multiplexer 4. The source of the address transfer to block 1 depends on the state of input 80. Information can be written to register 3 without copying in block 1. This information can be used to modify the DC components in block 2 or to form short variable components on the CRT screen. in the fourth mode of operation of the device (containing no more than one line of text).

The copy accumulated in block 1 can be used to restore unmodified information about the original image in block 2 and to directly display information on the CRT screen in the fourth mode.

An external computer can also be a source of addresses of transmitted information. In this case, the signal from input 80 multiplexer 4 is switched to a mode in which a computer address bus is connected to the input of the block 1 sampling, instead of the outputs of the address counters of block 9. In this case, it is possible to write and read information in block 1 in any order, which is convenient in cases where only part of the image is modified and the 4Q modification speed should be high. If necessary, change the background image with a pulse from input 21 through the second element OR 18, the third register 16 is cocked according to its first input45 remote control. The signal from the output of the register 16 is supplied to the first input of the block 15 adders modulo two. As a result of the action of this signal, the signals coming from the first output of block 3 to block 2 are inverted. The action of block 15 continues until block 16 is reset by the pulse from input 20.

A variant of starting the block 15 through the block 9 of the control. In this case, the mode code is modified in register 14, for example, due to an additional bit, into which, in case of modification, the unit is written. .

Thus, the performance of the device is improved by eliminating the need to transfer large amounts of information during modification. A small portion of the image and providing the ability to display information in parallel with its transmission to the first block 1 of RAM.

Claims (1)

Formula of invention A device for displaying information on the screen of a television oscillator containing the first and second blocks of random access memory, the first, second and third registers, the first, second and third blocks of AND elements, the block of OR elements, the first and second OR elements, the permanent memory block, the raster line generator , a video signal generating unit, a control unit, · the first output of which is a sync output of the device, the second and third outputs are connected respectively to the sampling inputs of the first and second blocks of RAM, the fourth and the fifth outputs of the control unit are connected respectively to the first inputs of the first and second OR elements, the second inputs of which are the first and second control inputs of the device, respectively, and the outputs are connected respectively to the recording and reset inputs of a third register, the output of which is connected to the first information input of the unit modulo two adders, the second information input of which is connected to the first output of the first register, and. the output is with the information input of the second block of random access memory, the output of which is connected to the first information input of the first register, the second information input of which [is connected to the output of the third block of AND elements, and the control input is [the sixth output of the control unit, I, the seventh and eighth outputs of which are connected respectively to the first inputs of the first and second blocks of AND elements, and the ninth and tenth outputs, respectively, to the address input of the read-only memory block. And the control input of the raster line generator, the output of which is connected to the second input of the second block of AND elements and the first input of the third block of AND elements, the second input of which is connected to the eleventh output of the control unit, the twelfth output of which is connected to the clock input of the video signal generation unit, the output of which is is connected to the video input of the television indicator, and the information input is to the output of the block of OR elements, the first input of which is connected to the output of the second block of AND elements, and the second input is to the output of the first block of AND elements, the second input of which is connected to the second output of the first register, the third output which is connected to the control input of the permanent memory block, the output of which is connected to the information input of the raster line generator, the mode selector input of the control unit is connected to the output of the second register, the information input and input . the reset of which are respectively the third and fourth control inputs of the device, characterized in that, in order to increase the speed of the device, it contains a multiplexer, the first information input of which is connected to the second output of the control unit, and the output - to the sample input of the first random access memory block, information input -the output of which is connected to the information input-output of the first register and is the information input-output of the device, the address input of which is the second information input a multiplexer, the control input of which is connected to the input of the mode selection of the control unit and is the fifth control input of the device.