SU1575239A1 - Failure-proof memory device - Google Patents

Abstract

The invention relates to computing and can be used in the development of integrated memory chips, computers and devices. The purpose of the invention is to expand the field of application of the device due to the possibility of data correction. The fault-tolerant memory device contains a drive 1, a reference input 2, adders 3 modulo two, the first register 4, address 5 inputs, the first 6 input of the mode setting, multiplexers 7, information 8 outputs, demultiplexers 9, elements OR 10, second register 11, information 12 inputs and the second 13 input of the device operation mode setting. If a single failure (or defect) occurs, the memory is restored ("Good") and only if it fails again, it may lose its functionality ("Failure"). 2 Il.

Description

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The invention relates to computing and can be used in the development of integrated memory chips, computers and devices.

The purpose of the invention is to expand the field of application of the device due to the possibility of data correction.

Figure 1 shows the functional diagram of the device; Fig. 2 shows the servicing algorithm of the device.

The device contains a drive 1, an input 2 of treatment, adders 3 modulo two, the first register 4, address inputs 5, the first input 6 of the mode setting, multiplexers 7, information outputs 8, demultiplexers S, element OR 10, second register 11, information inputs 12 and the second input 13 of the device operation mode setting.

The device in the computer works as follows.

Periodically (i.e., as a result of cyclical calculations or as a result of a timer interrupt), the computer executes the subroutine in accordance with the service algorithm (Fig. 2).

At the beginning of the computer, it executes the block. Set the correction word of address 00 ... O. At the same time, the code 00 ... 0 will be set on the address bus or the device’s address inputs 5. After the active signal is output via the control bus, the signal goes to the first input 6 sets the device mode, as a result of which the code 00 ... 0 will be written into the first register. Then the computer executes the program block. Set the data correction word 00 ... O. This process proceeds similarly, with the only difference that the code 00. .. About issued on the data bus and enters the information ionic input device 12, and the active control computer bus signal supplied to the second input 13 of device specifying mode. As a result, the code is written to the second register 11. By performing these operations, the device sets the initial state. At the same time (since at the first inputs of adders 3 modulo two zero potentials are installed from the outputs of the first register 4) the address from the address inputs 5 of the device to the address inputs of the accumulator 1 passes unchanged. Since the control inputs of the demultiplexers 9 also receive zero potentials from the outputs of the second register 11, the computer data bus bits from the information inputs 12 of the device will flow through the first outputs of the demultiplexers 9 to the main information inputs of the drive 1. In this case, the outputs eight

devices multiplexers 7 connect the main outputs of accumulator 1, since zero potentials are also established at the control inputs of multiplexers 7.

Then the program block is executed.

Test the working memory area. In the process of executing this fragment of the service program, the computer performs a non-destructive test of the working area (it is assumed that there is at least one unused cell in the address space). As a result of the test, several situations are possible, which are analyzed by the following program blocks. If, as a result of executing the Memory block, it is found out that this fact takes place, then the Display indicator block is executed correctly and the service subroutine ends. Otherwise, a Defect of Defect- check occurs. If the test result is negative, then an address defect occurs, so the procedure for selecting the address correction word is implemented. This procedure consists in the cy-k5 lyrical repetition of blocks Address correction word 111 ... 1, Increment the address correction word. In each cycle of this procedure, the address correction word is changed.

0 in the first register 4. As a result, the address of the defective cell of drive 1 is changed relative to the frame inputs of the Device due to the action of adders 3 modulo two. This will continue until

5 until the defective cell of accumulator 1 is pushed into the unused area of the address space, i.e. The memory workspace will show that the memory is in good condition or until all possible combinations of the address word have been exhausted. In the latter case, it is impossible to recover. (for example, a defective zone is wider than an unused memory zone) and therefore the Block Failure block is executed, if in

5, during the execution of the block, you find that there is a defect in the discharge of accumulator 1, then the computer will proceed to perform data correction operations. First of all, it is necessary to check whether the additional bit is used. This is done during the implementation of the block Data correction word 00 ... O. The defect detected by the test can be eliminated by executing Set 1 in the defective correction word of the correcting data word. As a result, the demultiplexer 9 and multiplexer 7 corresponding to the defective discharge will be switched. The corresponding discharge of the information inputs 12 of the device through the second output of the demultiplexer 9 and

Claims (1)

the element OR 10 is connected to the auxiliary information input of the accumulator 1, and the auxiliary output of the accumulator 1 through the corresponding multiplexer 7 is connected to one of the outputs 8 of the device. In other words, the replacement of the defective bit of drive 1 with an additional one will occur. Thus, if a single failure (or defect) appears, the memory operability is restored (Is), and only if it fails again, it can cause a loss of functionality. The invention Failsafe memory device containing a drive, the input of which is the device of the same name, modulators two, the outputs of which are connected to the accumulator address inputs, the first register, the outputs of which are connected to the first inputs of modulators two, information - the input inputs of the first register are connected to the second inputs of modulo-two adders and are the device's address inputs, the synchronization input of the first register is the first input of the device mode setting In order to expand the field of application of the device due to the possibility of data correction, demultiplexers, a second register, an OR element and multiplexers by the number of accumulator bits are entered into it, the multiplexer outputs are information outputs of the device, the first information inputs of multiplexers are connected with the outputs of the accumulator, the second information inputs of the multiplexers are combined and connected to the output of the additional discharge of the accumulator, the first outputs of the demultiplexers are connected to the information the storage inputs of the accumulator, the output of the OR element is connected to the input of the additional information bit of the storage drive, the inputs of the OR element are connected to the second outputs of the demultiplexers, the outputs of the second register are connected to the control inputs of the multiplexers and the demultiplexers, the information inputs of the second register are connected to the information inputs of the demultiplexers and are information the inputs of the device, the input of the lowering of the second register is r-op: ui input of the setting mode of the device (Nacha / toj tftitir iff t kohvekt ruashe address words