SU1559346A2 - Dividing device with self-check - Google Patents

Abstract

The invention relates to automation and computing, can be used in the construction of operational blocks of digital devices and is an improvement to the device by A.c.cccpN1483455. The purpose of the invention is to increase the reliability of the control device. The device contains a residual register 1, a divider 2 register, a multiplier 3, a memory block 4, a switch 5, a subtracting counter 6, a trigger 7, elements AND 8.16, an adder - subtractor 9, a register 10 private, register 11 reference, the element OR- NOT 12, control block 13, counter 14 cycles, bit comparison block 15, elements OR 17,18. The control of the device is carried out by checking the correctness of the operation of the memory block 4, the output of which should not contain a zero code in the P bits, and by comparing on the block 15 the equality of the states of the register 10 private and the register 11 of the reference. 3 il.

Description

one

(61) 1483455

(21) 4363703 / 24-24

(22) 10/24/87

(46) 04.23.90. Bul Number 15

(72) A.I.Bobrovsky, A.V. Voevodin,

D.V.Melaev and A.M.Trubitsyn

(53) 681.3 (088.8)

(56) USSR Copyright Certificate ff 1483455, cl. G 06 F 11/00, 1987.

(54) DEVICE FOR FISSION WITH SELF-MONITOR

(57) The invention relates to automation and computing, can be used in the construction of operational blocks of digital devices and is an improvement of the device according to the USSR author No. 1483455, the purpose of the invention is to increase the reliability of control of the device. The device contains a residual register 1, a divider register 2, a multiplier 3, a memory block 4, a commutator 5, a subtractive counter 6, a trigger 7, elements AND 8, 16, adder-subtractor 9, a register 10 private, register 11 reference, element OR - NOT 12, control unit 13, counter 14 cycles, bit comparison unit 15, elements OR 17, 18. The device is monitored by checking the correct operation of memory block 4, the output of which should not contain a zero code in the digits and by comparing on block 15 the equality of the states of register 10 private and register 11 reference. 3 il.

and s

The invention relates to automation and computing, can be used in the construction of operational blocks of digital devices and is an improvement of the invention according to the author. No. 1483455.

The aim of the invention is to increase the reliability of the control device.

FIG. 1 is a functional diagram of the device j in FIG. 2 is a state transition graph and control unit outputs; in fig. 3 is a functional block diagram.

The device for dividing with self-control (Fig. 1) contains the remainder 1 and divider 2 registers, multipliers 3,

memory block 4, switch 5, subtractive counter 6, trigger 7, second element AND 8, adder-subtractor 9, registers of private 10 and reference 11, OR-NOT 12 element, control unit 13, counter 14 cycles, bit 15 comparison, first element AND 16, elements OR 17 and 18.

i

The control unit 13 (Fig. 3) contains the triggers 19-22, the elements OR 23 and 24, the elements AND 25-29, the elements 30-32, delays, the inputs and outputs 33-40 of the block.

The device works as follows.

In the initial state in the register 2 there is a divisor, in the lower bits of the register 1 - a dividend, counter 14

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4 00 4b O

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is in the initial state (zeroed or an addition code is written in it), trigger 7 is zero (in the inverse output there is a single signal allowing writing to the register 11 of the standard). On the Start signal, signifying the beginning of the division operation, the control unit 13 goes from state A0 to state A. The contents of counter 14 are incremented by one (j + 1), the initial dividend in register 1 is shifted, with the result that in register 1, the next dividend is formed. Then, according to the value of the corresponding high-order bits of the divider and the next dividend, coming from registers 2 and 1 to the corresponding bits of the address input of block 4, the p-bit code is selected, which is the preliminary value of the next private bits.

The code of the preliminary value of the quotient is fed to the input of the multiplier 3, the contents of the p bits of the code of the preliminary value of the quotient are input to the subtractive counter 6 and the inputs of the p input element OR NOT 12. If the values of all the p bits of this code are zero then the output of the element ORI 12 is in Wits 1, which enters the input of the two-input element AND 16, the second input of which receives 1 from the output 34 of the control unit 13, and the output of the element 16 and 16 - 1, indicating the error or block 4 failure.

Then block 13 transitions from state A to state At. In this case, the code selected from block 4 is multiplied in multiplier 3 by the divisor, and the p bits of the code are written to subtractive counter 6. The product obtained in multiplier 3 is subtracted in the subtractor 9 from the next divisible, and the result (the next the remainder is recorded in register 1. If the next remainder is non-negative, the control unit 13 goes from state A2 to state A4, a record of private bits in frequency registers 10 and reference 11 is recorded, and then the values of the next private bits by appearance Igna stop from the counter 14.

The record of the reference register 11 is made only in the first cycle of the performing operation. If the counter of the 14 cycles contains the addition code

j + 2, to the trigger input. 7, 1 translation trigger 7 is sent to a single connection. At the inverse output of the trigger 7, there is a zero signal that prohibits writing into the register 11 of the standard, at the forward output of the trigger 7-1, which is fed to the input of the And 8 element.

If in any cycle the next residue turns out to be negative, then the control unit 13 switches from state A2 to state A. This means that the code selected from unit 4 is one unit lower than the true one. Therefore, the contents of subtractive counter 6 is reduced by one and a divider is added to the contents of register 1 using adder-subtractor 9 (the remainder is restored). Next, the control unit 13 goes to state A, and the division cycle is repeated.

If in any dividing cycle the values of the p bits of the pre-private code are 0, then the output of the AND 16 element is a 111 signal, indicating an error or a malfunction in block 4. From the output of the AND 16 element, the error signal goes to the input of the element OR 18, at the output of which a signal 1 appears, indicating a device error.

Upon the occurrence of the Stop signal from the counter 14 cycles, a signal 1 appears at the output of the element And 8, allowing the reading of bits Zj4. ..Zj of the quotient from the register of 10 quotients and the ZM bits. Z1p of the reference value from the register of 11 benchmarks, and a comparison is made of Z ,, ... Z4pH z r ..z p by block 15 of the bit comparison. On the Stop signal from the counter of 14 cycles, the block 13 goes from state A to state A0, and the Reset signal resets the counter to 14 cycles and trigger 7. If the values of Z, {. . , Z, p and ZH. ..Z {pHe coincide, it means there was a failure or failure in the operation of register 10 private, and at one or several outputs of block 15 there appears a single signal that is fed to the inputs of the p-input element OR 17 at the output of the element OR 17 - 1, input to the element OR 18; at the output of the element OR 18 - a single signal indicating a device error.

Claims (1)

Formula invented leaks A device for dividing with self-control according to the USSR USSR No. 1483455, which is based on the fact that, in order to increase the reliability of the control, a second And element, two 1ShI elements, a trigger, a standard register and a bit comparison block were inserted into the device, the first the output of the control unit is connected to the zero input of the trigger, the inverse output of which is connected to the input of the record of the standard register, the output of which is connected to the first information input of the one-bit comparison unit, the second information input of which is connected to the information output of the register Istra private, per15 1550346 five the second input of the second element And the clock input of the bit comparison block are connected to the overflow output of the cycle counter, the forward trigger output is connected to the second input of the second And element, the output of which is connected to the read inputs of the private register and the standard register, the outputs of the bit comparison block are connected to the inputs of the first OR element, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the first element -and, the output of the second discharge of the cycle counter is connected to the unit trigger trigger, the output of the second element OR is the error output of the device. FI.1 / 7 # hl } (At} (A , W OST e V- JSTTa / T Stop iff ,BUT .With o -f It i fft /. Ocftj. 4. Q 2