SU736097A1 - Squaring arrangement - Google Patents

Description

one

The invention relates to computing and can be used in digital computing and functional devices, digital with measuring devices, as well as for processing information represented by number-pulse codes.

There are known quadrators that use the time-pulse transformation 1 and 1.

The disadvantages of the known devices include the complexity of their circuit implementation, due to the significant number of elements of discrete technology, counters, logic circuits, pulse distributors, key circuits, the need for multi-cycle recording and rewriting devices20

binary codes. The presence of a complex scheme reduces the reliability of known devices.

The closest ones by technical

- to the essence of the proposed is 25 a device for squaring, containing a delay element and a pulse doubler, connected by inputs to the information input of the device, and the output of the doubler im-zO

pulses connected to the input of a binary counter 2,

In addition, the device contains key recording circuits, a one-shot, pulse distributor, and a fixation counter. The device is based on the implementation of dependencies.

li-3 + 5t ... (2m-lj m -. (2i-l) (i)

It makes it possible to obtain the square of the number m by organizing the sum of m-odd numbers of positive integer p.

The disadvantage of the device is the complexity of the circuit implementation, due to the presence of two pulse counters, one-shot, pulse distributor.

The purpose of the present invention is to simplify the device.

The goal is achieved by the fact that in the device for squaring, containing a delay element and a pulse doubler, connected by inputs to the information input of the device, and the output of the pulse doubler is connected to the input of a binary counter, an adder and I elements are entered, the first inputs of which are connected to

.outputs binary counter, the second .inputs - with the release of the delay element. and outputs to the inputs of the adder.,

In the binary counter, before starting, a preset is made to (), where n is the number of bits of the binary counter. This makes it possible to replace the operation of forming a sequence of even numbers in a cumulative counter of a known device by the operation of forming a number of odd numbers in the proposed device. As a result, there is no need in the distributor for them, pulses, performing a consistent poll of key recording circuits and a one-shot, which simplifies the circuit.

The drawing shows a device for squaring.

The device contains informational input 1 of the device, a doubler of 2 pulses, a delay element 3, a binary counter 4, elements AND 5, an adder b.

The device works as follows.

All bits of binary counter 4 are preset to the state, i.e. the number () "is recorded." The number-pulse code Nj starts to arrive at the input 1 of the device. The first input pulse N,, passes through doubler 2, in which it is converted into two pulses N

and N

enters the binary input

count 4. Pulse N, causes overflow of counter 4, i.e. all bits are set to state O. A pulse NI writes to counter 4. . The input pulse N is also fed to the input of the delay element 3, the delay time Tj of which is longer than the time required to convert the pulse N to the pulses Nj and N in pulse doubler 2 (T), binary counter 4 overflow (TD) and write 1 in the same counter (T,), i.e.

(2)

H - T2 + T,

V / T,

one

So after recording

the binary counter 4 to the second inputs of the elements And receives the enabling signal from the delay element 3, pulse N, and the code from the binary counter 4 is copied to the adder b. After the first input pulse N, the number is written in the adder 6.

The second input pulse NJ, passing through pulse doubler 2, is converted into pulses Ng and NJ, which arrive at the -input of a binary counter 4. These pulses Nn and Nj are summed with the previously recorded unit: danitsa and binary counter 4 records the number three in binary code. Then this code (the number three) through the elements And, on the first round of the x-ths, the enabling pulse N, delayed by the delay element 3, is rewritten into the accumulator 6. In the adder 6, the binary code of the number three is added with the one recorded earlier and is set the result is number four; thus, in the adder 6, after the input pulse N, the number NJ 4 is written.

The third input pulse N, after passing through the doubler 2 pulses, is converted into pulses NJ and NJ, which arrive at the input of the binary

N

counter 4. These pulses are N and

summed with the previously recorded code of the number three, and the number is written in binary counter 4

the code (five numbers) through the elements AND, the first inputs of which receive the tracking pulse N. delayed by the delay element 3, is rewritten into the adder where the binary code of the number five with the number three recorded earlier is added and the result is set - the number of nine be So after the third input pulse N,

the adder is recorded. chi ate

N, 9

For the NI th input pulse, the squaring process is similar. The current value of the binary racla at time tj, recorded by counter 4, is equal to

one

N;

where, 2 ,,. ,, m is the number of input pulses. The sum-mountain readings are equal at the same time.

(21-)

one

where m is the number of input pulses, in a square.

The proposed device, in comparison with the known one, has been simplified due to the failure of the one-shot and pulse distributor, which performs the sequential polling of the binary bits of the cumulative counter.

 the invention

A squaring device, containing a pulse doubler delay element, connected by inputs to the information input of the device, and a pulse doubler output connected to a binary counter input, characterized in that, for the sake of simplicity, it contains an adder and I elements, the first inputs of which are connected to the binary outputs of the binary counter, the second ..

inputs - with the output of the delay element, and outputs - with the inputs of the adder,

Sources of information taken into account in the examination

1. USSR author's certificate No. 432492, cl. G06 F 7/38 1972.

2. Authorship certificate of the USSR No. 438989, cl. General F 7/38, 1973.

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Claims (1)

Claim Device For squaring, containing a delay element and a pulse doubler, connected by inputs to the information input of the device, and the output of the pulse doubler is connected to the input of a binary counter, different ’. the fact that., in order to simplify, it contains an adder and AND elements, the first inputs of which are connected to the binary outputs of the binary counter, the second. input - with the output of the delay element, and the output with the inputs of the adder.