SU1536511A1 - Device for decoding codes with minimum redundancy - Google Patents

Abstract

The invention relates to telecommunications and can be used in facsimile systems. The invention decodes a code with minimal redundancy (for example, a Huffman code) without storing in the block 6 values of the size of each codeword, which simplifies the device. The device comprises a marker allocation block 1 (end of line), an address driver 2, a pulse distributor 3, an OR 4 element, a group of flip-flops 5, a permanent memory block 6 and a code converter 7. 1 il.

Description

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The invention relates to telecommunications and can be used in facsimile technology, in particular in the systems of the G3 group recommended by CCITT.

The purpose of the invention is to simplify the device.

The drawing shows the functional diagram of the device.

The device contains a marker allocation unit (end of line) 1, an address generator 2, performed on the pulse distributor 3, the OR element 4 and the trigger group 5, -5 cm, the permanent memory unit 6 and the code converter 7.

The device works as follows.

Preliminarily, in block 6, the value of the decoded value is recorded at the address for which the code word from the Huffman code tables is used, at the end of which one is added followed by zeros. If the codeword bit is less than the maximum value, then the codeword +1+ zeros is used as the address. Therefore, if the code word in the low-order bit has a zero bit, in order to exclude its influence on the correctness of the information conversion in block 6, the input address for the latter must be a code word with a unit added to it.

The sequence of binary data, followed by a clock frequency, is fed to the address generator 2 and the marker selection block 1.

Block 1 can be made of a serial register, the outputs of which are connected to the input of the decoder, the latter and forms a pulse from the binary data stream, characterizing the presence of a code word at the end of the line. The generated pulse from the output of block 1 sets to the zero state through the element OR 4 of the distributor 3 and triggers 5. After that, the code word of the bit starting from the highest bit is written to the triggers 5 by means of the distributor 3, at the input of which clock pulses This is each i-th (, 2, ..., p) output of the distributor 3 connected to the clock input of the 1st trigger 5, and also starting from i 2 connected to the set-up

5 5

0

0

h 0

input (i + 1) ro trigger 5, records an additional bit as a unit on the installation input remote control S.

Thus, in block 6, at the address defined by a codeword with an additional unit, the length of a series of image elements of a facsimile string with a binary code can be written. The appearance of information at the output of block 6 is the start of operation of the converter 7, which may consist of a processing start forming unit, a register and a code conversion unit into the number of pulses that go to the output. When information appears at the output of block 6, the signal from the processing start block (from the element 6 with the synchronization circuit connected to the outputs of block 6) rewrites the information from block 6 to the register of converter 7, starts converter 7 and clears the address generator 2. Shaper 2 addresses receives the next code word is similar to the reception of the previous code word.

Claims (1)

Thus, the device allows decoding a code with minimal redundancy (for example, a Huffman code) without storing in block 6 the magnitude of the size of each codeword. Invention Formula A device for decoding codes with minimal redundancy, containing a pulse distributor, the clock input of which is the clock input of the device, a group and n + 1 flip-flops, where n is the code width and the OR element, the outputs of the pulse distributor except for the first and +1) -th bit, connected to the installation inputs in 1, respectively, of the first (n-1) -th group triggers, characterized in that, in order to simplify the device, a fixed memory block, a code converter and a selection block are entered into it marker, the first entry which a clock input connected to the device, the second input is combined with the data inputs of flip-flops and the group is a data input device ayde- laziness marker block output is connected to the first input of the OR gate, whose output is connected to the distribution installation entrances 51536511 pulse limiter and trigger memory, the outputs of which connectors, clock inputs trigger with the same inputs of the conversion group are connected to the outputs of the same name code, the first and second outputs pulses distributor, which are respectively connected to the outputs of the group triggers are connected to the second input of the OR element and are the same-name inputs of the constant-n output device.