SU1532979A1 - Read-only memory with self-diagnosis - Google Patents

Abstract

The invention relates to computing and can be used to create reliable high-speed memory systems based on large integrated memory chips with a word organization. The purpose of the invention is to increase reliability by fixing errors that occur in two memory modules at the same time. The device contains an address block, an accumulator, first and second adders, private syndromes calculating blocks, comparison blocks, AND group of elements, modulo two adders group, switch, additional comparison block, first, second, third OR-NOT elements, I. into the device of an additional unit of comparison, the elements OR-NOT and the element AND allows to correct any single failures of the memory integrated circuits in each word of the accumulator and detect errors caused by two or more imps failures in the word by analyzing then the first and second adders and outputs of the comparison units. 2 Il.

Description

The invention relates to computing and can be used to create reliable high-speed memory systems based on large integrated circuits with a word organization.

The purpose of the invention is to increase reliability by fixing errors that occur in two memory modules at the same time.

The drawing shows a schematic diagram of a self-monitoring permanent storage device.

The device contains the address block 1, drive 2, outputs 3 data bits, outputs 4 and 5 control bits, the first adder 6, the second adder 7, blocks 8 for calculating private syndromes, the U blocks for comparison, the group of elements I 10, the group of adders P through module two, switch 12, additional comparison block 13, first J4, second 15, third 16 OR-NOT elements, AND 17 element.

The device uses modular codes for error detection and correction. The memory is built on semiconductor devices with multi-bit (V-bit) organization. The word stored in the accumulator is divided into N groups of characters (modules), B characters in each group. To detect

ate

with

N9

0 j

WITH

31532979

and correcting a single UTI failure in a word requires B + N additional bits.

The check matrix has a vice

mind

2 neither but

H

ABOUT

s B + 2;

- unit matrix of order B;

- zero matrix of order B;

- matrix obtained from L

cyclically shifting all B + + 1 lines of it by i lines down and dropping the last line, and

G 0000 ... 0 1 I P J

The device corrects any single UTI failures in each word of the accumulator and detects errors caused by two or more ISH failures in the word. The detection of errors caused by two or more FIL failures in the accumulator word is performed by analyzing the states of the first and second adders and the output signals of the comparison blocks.

The device works as follows.

Example 1. Let message 2 of length K be stored in drive 2

 16 bits, and B

/ Xt16

4, then N -, -

 4. The test matrix will have

view

H

24.6

check bits are stored in two additional modules of drive 2. The message 0000 0000 1000 0001 will be stored in drive 2, taking into account the check bits as 0000 000

10000001 1001 1010.

Let the information be distorted in the 1st module, i.e. 1100 0000 1000 0001

10011010.

At the output of the first adder 6, the state (syndrome S) is 1100; at the output of the second adder 7 (S2 syndrome), the state is 0110.

The 8 individual partial syndrome calculations (multipliers) perform the operation.

five

0

multiply S S, L, where,

2, 3, 4, and at the output of the blocks for calculating private syndromes 8, respectively, the codes appear:

S 0110

S 001 1

S 1001

h &

1000

On the second inputs of the first block 9

comparison is the ONE code, then a logical one is set at the output of the first comparison block 9, since the codes are the same.

5 Consequently, on the second exits

the corresponding elements of V 10, connected to the output of the first comparison unit 9, are formed p thrashing. The signal and code of syndrome 5 are transmitted through modules I 10 to the first inputs of adders 11 modulo two, to the second inputs of which distorted information is received from accumulator 2. As a result of adding modulo two

5, by the syndrome code S, the information is restored and through the switch 12, if there is a signal at its control inputs, it arrives at the information output of the device.

0 Since on the first and second outputs

Additional comparison unit 13 information is different (syndrome code P 1100 and syndrome code S2 0110); a zero signal is generated at its output. At the same time, the output of the first element IPI-NO 14 is set to a zero signal, since its inputs receive the syndrome code S, other than zero. A logical unit is set at the output of the third element OR-NOT 16 (a signal fixing the error), but due to the fact that a logical zero is formed at the output of the second element OR 15, the device does not generate an error signal.

Example 2. Suppose that for the above example the information was distorted in the first and second modules, that is, 1100 0010 1000 0001 1001 1010, then S syndrome, 1J10 - output of the first adder 6, syndrome S2 0110 - output of the second adder 7.

five

0

five

At the outputs of blocks 8, the calculation of private syndromes. The codes are formed:

sr

S

with

ъъ

h a +

01 11 UN 1001 1100,

which arrive at the first entrances

units 9 comparison, the second inputs of which in this case receives the code of the syndication device, the outputs of the address block

connected by garden entry

Roma S - 0110. At the outputs of all blocks, the first and second L-bit dnyr

For comparison, a logical zero is established, since the syndrome code 0110 does not coincide with any of the codes of particular syndromes.

Since the codes of syndromes St - 1110 and B - 0110 are different at the first and second inputs of the additional comparison block 13, a logical zero is formed at its output. At the same time, a zero signal is generated at the output of the first element OR-NOT 14, since the syndrome code S. is different from zero. At the second input of the element And 17, a logical unit v is established (a signal that fixes errors in two modules).

At the first input of the element And 17 a logical unit is also established, since zero signals are fixed at the inputs of the second element OR-NOT 15. At the output of a self-monitoring permanent storage device — the element output 17 — an error signal appears that the device cannot correct. Since the transfer of S syndrome to adders 11 modulo two is blocked by AND 10 elements, the logical inputs of which are generated at the second inputs are not corrected, in this case the information transmitted from accumulator 2 is present at the output of switch 12.

Compared to the prototype, the reliability of the self-monitoring storage device is higher due to the possibility of recording errors occurring in two memory modules simultaneously by comparing the codes of two syndromes, as well as analyzing the results of comparing private syndromes with the code of one of the syndromes. In this case, the speed of the device is saved.

Claims (1)

Invention Formula Permanent self-monitoring storage device containing a drive consisting of storage elements of a size b, address ten 20 25 thirty adders, computing units are private syndromes, comparison units, elements I, modulo-two adders, a commutator, with the inputs of the first and second adders connected to the outputs of information and test bits to the accumulator, the outputs of the first summat are connected to the inputs of the blocks calculating private syndromes, output The 15th block of calculation of private syndromes (where l ... b) is connected to the first inputs of the tth comparison block, the second inputs of the comparison blocks are connected to the output of the second adder, the output of the mth comparison block is connected to the first inputs of b (t - 1) + i elements AND (where i l ... b), the second inputs of the elements I are connected to the corresponding output of the first adder, the outputs of the elements are connected to the first inputs of the adders modulo two, the second entrances of which are connected to the corresponding and formational outputs of the accumulator, the outputs of the adders modulo two connectors with information inputs to the mutator, the control inputs of which are connected to the inputs of the address block; the outputs of the switch are information outputs of the device, which are different in that, to increase the reliability of the devices, the element I is added to it, an integral comparison unit, the first, second and third elements OR NOT, and the inputs of the first element OR NOT are connected to the first group of inputs of the additional comparison block and the outputs of the first adder, the inputs of the second element OR NOT are connected to the outputs of the comparison blocks, second the group of inputs of the additional comparison unit is connected to the outputs of the second totalizer, the first input of the third element OR is NOT connected to the output of the complementary comparison unit, the second input of the third element OR is NOT connected to the output of the first element OR NOT, and the output It is connected to the first input of the AND element, the second input of which is connected to the output of the second element OR, and the output is the output of the device error signal. 35 40 45 50 55 15329796 unit whose inputs are inputs devices, address block outputs connected by sadresnye inputs 0 five 0 adders, computing blocks of private syndromes, comparison blocks, elements I, modulo-two adders, a switch, with the inputs of the first and second adders connected to the outputs of the information and test bits of the accumulator, the outputs of the first adder connected to the inputs of computing blocks of private syndromes, output m the first block 5 of the calculation of private syndromes (where ha l ... b) is connected to the first inputs of the t-th comparison block, the second inputs of the comparison blocks are connected to the outputs of the second adder, the output of the m-th comparison block is connected to the first inputs b (t - 1) + i elements And (where i l ... b), the second inputs of elements And are connected to the corresponding outputs of the first adder, the outputs of elements And are connected to the first inputs of modulo-two adders, the second inputs of which are connected to the corresponding information outputs the accumulator, the outputs of the modulo-two adders are connected to the information inputs of the switch, the control inputs of which are connected to the inputs of the address block, the outputs of the switch are information outputs of the device, characterized in that, in order to increase the reliability devices, an element I, an additional comparison block, the first, second and third elements OR NOT are entered into it, the inputs of the first element OR NOT are connected to the first group of inputs of the additional comparison block and the outputs of the first adder, the inputs of the second element OR NOT are connected to the outputs of the comparison units, the second group of inputs of the additional comparison unit is connected to the outputs of the second adder, the first input of the third element OR is NOT connected to the output of the additional comparison unit, the second input of the third element OR NOT the connection ene with output of the first OR-NO element, and an output coupled to the first input of the AND gate, a second input coupled to an output of second OR- NO element, and the output is the output of the error signal. five 0 five 0 five