SU1495799A1 - Signature analyser for detection of intermittent faults - Google Patents

Abstract

The invention relates to the technical diagnostics and can be used to search for intermittent faults during adjustment and repair of digital computers and instruments. The purpose of the invention is to reduce the time for troubleshooting. The signature analyzer comprises a probe 1, an input block 2, a pulse sequence control block 3, a fault recording block 9, a measurement window setting block 12, a control block 17, and four display blocks. The signature analyzer allows you to determine the presence of a moving fault in long-length pulse sequences in one measurement, to determine the time when an intermittent fault appears by changing the length of the monitored portion of the pulse sequence. In this case, depending on the selected units of the length of the pulse sequence, the location of the malfunction is determined in stages, for example, in the processor first with the accuracy of the last transition, then with the accuracy of the command, then with the accuracy of the synchrotact. This shortens the search time for the first distorted character in the pulse sequence. 5 il.

Description

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c Reducing the time required for malfunctions. The signature analyzer comprises a probe 1, an input block 2, a pulse sequence control block 3, a fault recording block 9, a measurement window setting block 12, a control block I7 and four indication blocks. The signature analyzer allows you to determine the presence of a moving fault in large-length pulse sequences in one measurement, to determine the time of the occurrence of an intermittent fault.

by changing the length of the monitored portion of the pulse sequence. In this case, depending on the selected units of the length of the pulse sequence, the location of the malfunction is determined in stages, for example, in the processor, up to the last transition, then up to the command, then up to the sync tact. This shortens the search time for the first distorted character in the pulse sequence, 5 Il ,.

The invention relates to the field of technical diagnostics and can be used to search for intermittent faults during adjustment and repair of digital computers and devices.

The aim of the invention is to reduce the time for troubleshooting.

Fig, 1 shows the structural and functional scheme of the proposed analyzer; FIG. 2 is one of the implementations of the control pulse shaping implementation; FIGS. 3-5 are time diagrams explaining the principle of operation of the analyzer.

The signature analyzer (FIG. 1) contains a probe 1, an input block 2, a pulse sequence control block 3 containing a modulator A adder 2, a shift register 5, a signature storage register 6, a fourth indication block 7, a comparison block 8, a recording block 9 fault, containing the counter 10 and the first display unit 11, the block 12 specifying the measurement window, containing decimal counters 13.1,., 13, p, decoders 14.1,., 14, p, switches 5.1, ,,, 15 , p, the second block 16 of the display, block 17 controls - Ne, containing the triggers 18-20, elements AND 21-25, elements ПТИ 26-28, elements И-ИЛ 29-31, the control unit 32 generating pulses, the third display section 33, the switches (toggles) SK 34, lock / stop 35, the switches (buttons) CGpo. 36, Setting O 37, slots 38. and 39, The input block 2 in the simplest case may consist of one D-flip-flop 40 The control pulse-shaping block 32 (FIG. 2) contains the flip-flops 41 and 42, delay elements 43 and 44 and the element NOT 45,

The hardware implementation of the signature analyzer is produced by a shift register 5 with feedbacks through an adder 4, the outputs of the shift register 5 are connected to the inputs of the signature storage register 6 and a group of inputs to the comparison circuits 8. The outputs of register 6 are connected to the group of inputs A of the unit 8 of the comparison.

The unit 12 for specifying the measurement window also serves to determine the length of the monitored process from the start signal until the occurrence of an intermittent fault in the selected units of measurement (the branch points of the program, commands, sync pulses). To avoid errors in determining the length of the process being monitored, the last decade overflow (counter 1Sm) is output to the display unit 16, which has memory elements. Information recording in the display unit 16 can be performed either permanently or at the moment of resetting the trigger 18 Start. The setting of the measurement window is carried out with the help of switches 15.1., 15. 15.p and decoders 14.1 ,,. 14.p,

. The control of the pulse sequence always starts from the Start signal. Signal formation The launch, as a rule, is carried out with the help of a special triggering unit, which is constructed according to well-known prints.

Dp simplify the startup block, the elements of the synchronization signals Running

514

Stop with sync pulses on flash. 1 not shown.

Trigger 18 START generates a measurement window. Setting in one state the trigger 18 The start-up is always made from the Start signal, and the installation in the zero state, depending on the operating modes or on the overflow signal of the measurement task block 12, or on the Stop signal, either the trigger 18 Start-up operates in the counting mode

Trigger 19 The end of the pulse sequence (TRS) signals the operator about the end of the cycle if, when defining the measurement window using the switches of block 12, the next cycle is captured (i.e., the measurement window is longer than the cycle length). In addition, using the trigger 19 End of the pulse sequence. It is possible to limit the length of the process to be controlled. To do this, during the operation of the analyzer, the value of the switch 15 is increased until the measurement window is larger than the cycle length. After that, the value of the switch 15.P is reduced by one and the selection of the value of the switch 15.P-, etc., is performed in the same way.

The trigger 20 Stop is used to read the signature when the monitored process fails and to stop the monitored device at the moment of fault detection, for which a single trigger output 20 Stop is connected to the socket.

The SI 34 toggle switch serves to separate the clock pulses. At position 1, information is received into the signature analyzer by SI 1, which is also used to form the measurement window. At position 2 of the toggle switch, the SAI receive information into the signature analyzer is carried out by SI 2, and the measurement window is formed by SI I. This separation of clock pulses allows you to gradually search for a fault location in the programs: first, the measurement window, set the branch points of the program and determine the location malfunctions up to the last transition, then up to a command, then up to a clock pulse.

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The toggle switch 35 determines the operation mode, the analyzer) with the stop by the fault, or with the stop lock. In the Locking mode, if a signature does not match, a malfunction signal is detected, but a faulty signature of an intermittent malfunction cannot be counted. This mode is used when configuring the analyzer, when the reference signature has not yet been obtained, and (Determining the location of the fault. Exposure of the monitored device to the mechanical effect, you can visually observe the moments of the malfunction. In the Stop mode, in the event of a signature signature mismatch, the analysis

stops,

torus

signature is faulty

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If a signature is defective at several stops due to a fault, it means that the fault always occurs in the same place of the monitored pulse sequence, which indicates the stability of the intermittent fault. Using the Failure Stop mode, the monitored device is also stopped at the time the malfunction occurs. To continue operation after stopping, you must press the Reset button.

Button 38 Installing O produces 5 sets of zero trigger 18 Start,

block 12 of the task of the measurement window, the shift resistor 5.

Using the switch 36, the length is set to the length of the monitored pulse sequence. At position 1 of switch 36, a signature is generated from the Start signal to the next Start signal. This mode is used when searching for fixed errors and for determining the cycle length. In position 2 of switch 36, a signature is formed from the Start signal, to the value set on the switches 15.1 ... 15P. In position 3 of switch 36, a signature is generated from the Start signal to the Stop signal, which is applied to the Stop terminal. This mode is also used to determine the length of the monitored process from the Start signal until the occurrence of a fault.

Jack 39 is designed to synchronize the oscilloscope.

FIG. shows the outputs of control block 17, designated 1-10, which have the following functional purpose: 1 - measurement window synchronization output, 2 - indication control output, 3 - measurement end input, 4 - signature generator synchronization output, 5 - comparison gating, 6 - gating the transmission of information, 7 - the output of the resetting unit for forming the measurement window, 8 - the output of the zero setting of the signature generator, 9 - the output of the reset of the fault counter, 10 - the input of the fault signal.

Before starting work, the analyzer and the monitored instrument are prepared for operation.

The preparation of a monitored device consists both in the selection of characteristic control points and points used as SI, and in the collection and processing of information on intermittent faults accumulated during operation, test program run, reconfiguration of the computing complex, and preparation of a cyclic program in which malfunction detected. A cyclic program can be composed of. the work program (or its parts) by supplementing it with teams to compare the results, issue an error message (if necessary) and transition teams. The greatest difficulty is intermittent faults in circuits not covered by hardware control, which manifest themselves as an irregular result. operations or incorrectly generated signs of the result of an operation or a false interrupt, transition, etc. signal occurred.

The consequences of such malfunctions appear much later than they occur. It is on such faults that the proposed signature analyzer is primarily oriented.

Consider the work of the signature analyzer on the example of the most complex fault. During the cyclic operation of the program, sometimes there is a failure, which consists in the transition of the program to the addresses of the data area, which causes a hardware failure using a valid operation code. The sequence of troubleshooting with a signature analyzer is as follows:

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the moment of analyzer start is determined;

the number of commands (length) from start up to the moment the malfunction occurs is determined;

verifies the correctness of the sequence of execution of commands on the program branch points (the sign of transition) from the moment of launch until the moment of the occurrence of a malfunction;

determines when an error occurs in a program transition;

The monitored instrument is stopped at the moment an error occurs and the result of the program is analyzed. A pulse sequence is intended for subsequent contruction, for example, a word line bit;

pulse sequence of one bit of the word line is analyzed. The location of the fault is determined to within a command;

the monitored device is stopped at the time of the malfunction, the result of the program execution is analyzed, the command is executed incorrectly and, depending on the nature of the malfunction, a pulse sequence is planned for the next control;

the command loops, the target pulse sequence is analyzed, the moment of the fault occurrence is determined to the SI, the fault location is searched by the circuit circuit with the precision of the chip output or the connection.

Thus, consistently approaching the location of the fault, it is localized

To determine the number of commands executed before the occurrence of intermittent faults, interrogation interrogation signals are sent to the input 1 of the analyzer, which are generated after the execution of each command and will be used during the operation of the analyzer as an SI. Switch 36 The length is set to the third position, the controlled program is started in a cycle. Only block 12 is used to determine the number of commands executed from the time the analyzer was started to the time it was crashed in the signature analyzer.

the malfunction signal from the output of the first bit of the counter 10 is faulty via the input 10 of the control block 17 and the And 25 sets the trigger 20

ten

analyze the program, the temporary position of the input signals selected by the SI, and achieve stability of the signature (in the program, eliminate random interruptions, take other SI, etc.).

If the signature is stable, then button 37 Reset through the output 9 of the control unit 17 sets the zero of the fault detection unit 9 and the signature analyzer is configured to look for the intermittent fault. The cyclic mode of operation of the monitored device continues until the program fixes the j or address bus. In the quality of SI et intermittent fault. After receiving the information, a signal should be taken that the presence of malfunction signals in the signature analyzer is checked. If the signature analyzer has detected a failure in the pulse sequence of program branch points, then it is necessary to determine the time when this fault occurred. On switches 15.1 - 15.P, a value equal to K / 2 is set. It starts up cycling. The length of the monitored pulse program, which is pressed by the button sequence, will be measured in commands and the signature analyzer in commands, and the information will be produced in control of the signal pulse sequence. Transition from the start signal to the execution of K / 2 commands. If a cyclic program interleaves an error about 20

A stop that stops a monitored device.

As a result of the analysis of the executed program, the indication of the registers of the monitored device and the results recorded in the memory are followed by a pulse sequence for subsequent monitoring. This may be some kind of register register, numbering information output to (numeric) address buses. To do this, the SI switch 34 is switched to position 2, and the sync pulses of information output are fed to the CM terminal 2 on the numerical bus of the device under control, and the reception sync pulses are separated on the AND-OR element 29 by the sync pulses of information output to the numeric bus. On the switch 15.1 ... 15.P, the length of the controlled portion of the pulse sequence does not change. Toggle switch 35 Lock / Stop is set to the Lock position, the cyclic program is started. By the reset button 37, the fault counter 10 is reset and intermittent fault is waited. When detecting the intermittent fault by the supervising program, the presence of a malfunction signal in the analyzer is checked and if the analyzer also detected a malfunction, the command that determines the malfunction occurs is determined by changing the length of the monitored section. Dp analysis of the reasons for the occurrence of a failure. Ultimately, a command is detected that fails, not detected by hardware control. Depending on the nature of the malfunction, a replaceable elemental signal is replaced, malfunctions in the signature analyzer, and in the presence of a malfunction signal, the length of the monitored section is reduced by a factor of 2 (and increases without) and the cyclic program is started. the place is defined with exact

transition

(for

stew to the last

this stage of localization).

The next stage of the intermittent fault localization is the analysis of the result of the program execution upon failure. For analysis, it is first necessary to stop the monitored device at the time of the failure. For this, analyzer socket 40 is connected to the trigger input. Stopping the monitored device, the cyclic program is started and pressing the button 37 Reset, the analyzer is set up. The toggle switch 35 Locks / Stops translates to the Stop position and waits for intermittent faults. In case of intermittent malfunction

the fault signal from the output of the first bit of the counter 10 fault on the input 10 of the control unit 17 and the element And 25 sets the trigger 20

howling or address bus. Sigma should be taken as the SI for receiving information. The length of the monitored pulse sequence will be measured in commands, and the information will be

A stop that stops a monitored device.

As a result of the analysis of the program performed on the indication of the registers of the monitored device and the results recorded in the memory, a pulse sequence is planned for subsequent monitoring. It can be any register bit, j number or address bus number. Sigma should be taken as the SI for receiving information. The length of the monitored pulse sequence will be measured in commands, and the information will be

20

Information issue in (numerical) address buses. For this, the SI 34 toggle switch is transferred to position 2, and the sync pulses of information output are fed to the CM terminal 2 on the numerical bus of the monitored device, while the information sync pulses of the address or address bus are separated on the AND-OR element 29. Sigma should be taken as the SI for receiving information. The length of the monitored pulse sequence will be measured in commands, and the information will be

taken on sync pulses issuing information to the numeric bus. The switch 15.1 ... 15.P does not change the length of the controlled part of the pulse sequence. Toggle switch 35 Lock / Stop is set to the Lock position, the cyclic program is started. By the reset button 37, the fault counter 10 is reset and intermittent fault is waited. When the intermittent fault is detected by the control program, the presence of a fault signal in the analyzer is checked and if the analyzer also detected a failure, then the command that performs the failure is determined by changing the length of the monitored section. DP of the analysis of the causes of a failure, it is necessary to stop the monitored device according to the failure of the faulty command. After the stop, an analysis of the causes of the failure is performed and it may be that the described localization process needs to be repeated and checked for one more pulse sequence. Ultimately, a command is detected that gives a failure that is not detectable by hardware control. Depending on the nature of the fault, replacement of replacement elements is carried out.

The window and measure 1i and trigger 18 of start, cnn, al. Starting in each cycle through AND 22, OR 27, output 7 of control unit 17 sets zero decimal counters 13.1 ... 13.P in the first cycle through And 24 sets the trigger 18 start. The sync pulses through the element 21, the output 1 of the control unit 17 are fed to the synchronous input of the measurement task setting unit 12. In each cycle, the Start-up signal zeroes the counters 13.1-13.p of the unit 12 for specifying the measurement window and the pulse counting starts again. Cyclic mode continues until a failure occurs. When an intermittent fault occurs, the monitored device stops (proceeding to the input of the measurement task unit 12, and through the AND-OR element 29 and the output A of the control unit 1 to the shift register register 5 and the synchronous input B of the trigger 41 of the input unit 2.

Reception of information will continue until the counters 13.1 ... 13.P do not count the K command values set on the switches.

Signal End of measurement window (input 3 of control block 17, FIG. 4 through AND-OR 30 elements, OR 28 installs a Start trigger into O (FIG. Av which closes AND 21 and stops the flow of SR into measurement task block 12 and shift register

ten

15

frame or hardware), SI feed pre-blocking the formation of pulses. eleven

thirty

35

is growing, and in the display unit 16 the number of the last commands will be recorded before the occurrence of a fault signal. If the number of commands executed from the start up to the moment 25 is greater than the limit value of block 12, which is determined by the overflow indication on the display block 16, then the analyzer start should be moved closer to the fault location, or reduce the monitoring cyclic program.

DP control of the pulse sequence of program branch points (the sign of the Transition) on the switches 15.1. ..15.P sets the K value of the length of the pulse sequence, which is defined in the previous operation.

Switch 36 Dpina device is set to position 2, toggle switch 34 SI to position 1, button 38 Setting O through element OR 28 sets start zero of trigger 18, start through element AND-OR 31 and output 8 of control block 17 is set to About register 5 receiving information, and through the OR element 27 and the output .7 of the control unit 17, the measurement task setting unit 12 nulls, the analyzer Shoop 1 is connected to the output of the sign The transition of the monitored device. A cyclic program is started. The trigger edge 18 Start (Fig. 4c) is set through the element 24 on the falling edge of the signal S1GGUSK (Fig. 46).

Sync pulses (Fig. 4a) through the element And 21 and the output 1 of block 17

40

The reset trigger 18 Pu generates two pulses that are shifted relative to each other. Comparison strobing - output 5 of control unit 17 and pulse Information transmission strobing - output of control block 17 (Fig. 4e). Since there was no information in the first cycle in register 6, then when comparing registers 5 and 6, block 8 is compared, block 9 of the registration of faults will fix the fault, but after the first cycle in register 6, the value of the signal will be recorded signal Run through the elements AND 24 AND-ILIi 31, the output 8 of the block 17, the control sets the zero offset register 5, and through the elements OR 27 and the output 7 of the control block 17

Novuka Zero Block 12 Set the window and measure. On the trailing edge of the trigger, a trigger 18 is set up, which allows for the reception of an information 5 formation. The operation of the analyzer is performed as in the first cycle, described earlier. At the end of each cycle, the obtained value of the signature is compared with the value of the signature of the previous cycle. The unit for registering faults is a fictitious signal, inequality of signatures. If, after switching on the cyclic mode, the fault registration block 9 continues to fix the signal mismatch signals, and the cyclic intermittent fault program does not detect, then the resulting signature is unstable. In this case it is necessary

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control inputs to the input of the measurement task setting unit 12, and through ;, the element AND-OR 29 and the output A of the control unit 17 to the synchronous input of the shift register 5 and the synchronous input B of the trigger 41 of the input unit 2.

Reception of information will continue until the counters 13.1 ... 13.P do not count the K command values set on the switches.

Signal End of the measurement window (input 3 of control block 17, fig.4g) through the elements AND-OR 30, OR 28 sets the Start trigger (fig.Av) into О, which closes AND 21 and stops feeding the SI into the measurement window setting 12 and shift register 5,

ten

15

on Block 32 forming pulses. eleven

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The reset trigger 18 generates two pulses that are shifted relative to each other. Comparison gating - output 5 of control block 17 and pulse. Transmission of information transfer - output 6 of control block 17 (Fig. 4e). Since there was no information in the first cycle in register 6, then when comparing registers 5 and 6, the comparison unit 8, the fault registration unit 9 fixes a fault, but after the first cycle in register 6, the signal value will be recorded, and in subsequent cycles the control signal Running through the elements AND 24, AND-ILIi 31, the output 8 of the control unit 17 performs the setting of the zero of the shift register 5, and through the elements OR 27 and the output 7 of the control unit 17, setting the zero of the measurement task setting unit 12. On the falling edge of the trigger, a trigger 18 is set, which allows the reception of information. The operation of the analyzer is performed as in the first cycle described earlier. At the end of each cycle, the obtained signature value is compared with the signature value of the previous cycle. The unit for registering faults is a fictitious signal, inequality of signatures. If, after switching on the cyclic mode, the malfunction registration unit 9 continues to fix the signature mismatch signals, and the cyclic intermittent fault program does not detect, then the resulting signature is unstable. In this case it is necessary

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(com (blocks, TZZop), If it is necessary to determine the accuracy with the accuracy of the chip output (or connection), then the boot command is looped (comparing the result and issuing an error message), the pulse sequence is monitored and monitored The analyzer should be started from the start of the controlled command, and the pulse sequences should be monitored until the microcommand End of operation. On the Start terminal, the microcommand Start of the operation is sent, and on the Stop terminal of the microcommand. operation, the SR 34 toggle switch must be set to position 1, and sync pulses of micro-commands are output to the SI terminal 1, switch 36 The length is transferred to position 3, and the O-trigger trigger 18 signals are switched on the AND-30 element. The analyzer sends the selected control signal. The command starts looping. The Start signal (Fig. 5b) sets the zero of the counters 13.1 -... 13.P and shift register 5, and the trigger 18 is set on the falling edge of the signal (FIG. 5c), which includes the analyzer in operation. At the end of the monitored operation, a Stop signal is generated (Fig. 5d), through the AND-OR 30 element, the OR 28 element resets the Start 18 trigger (Fig. 3c. By resetting the trigger 18 Start by the control pulse shaping unit 32. Comparison gating is generated, and Information transmission gating (Fig. 5d, e). On counters 13.1 ... 13.P, the number of SI pulses from the Start to the Stop signal, which is indicated by the display unit 16 after resetting the Trigger 18 Start, will be counted (FIG. ZH If in a controlled pulse sequence uncovered The fault is determined, the fault location is determined by changing the length of the monitored portion of the pulse sequence. On switches 15.1 ... 15.P, a value equal to half the length indicated by display unit 16 is set.Switch 36 The length is set to position 2, starts cyclic mode and method of changing the length of the controlled area

14

A search is made for the time of the military boot system. Additional information about the malfunction can be obtained by viewing the monitored signals by the oscilloscope. Jack 39 is used to synchronize the oscilloscope.

In a number of cases, it is necessary to determine the cycle length from the trigger signal.

Q until next signal Start, on. For example, if there are no hardware errors in the monitored program and it loops or an incorrect result is obtained. For this

A 5 signature analyzer has a special mode of operation when a signature is generated from the Start signal to the next Start signal. Switch 36 The length is translated into.

0 the first position, while the potential of the logical zero is applied to the second input of the element OR 26, the unit arm of the trigger 18 Start is connected to the inverse input of the element OR 26, the trigger with the counting input is connected. The operation of the analyzer in this mode is no different from that described above. Counters 13.1 ... 13.n counted the length of the controlled process in selected

0 units of measure, program branch points, instructions, measures, and this value will be displayed on display unit 16. The timing diagram of this mode is shown in FIG. 3. Here, a is the clock pulses, b is the start signal, c is 1TG Start, d is the comparison, e is the transmission from P5 and P6, e is the indication of the clock counter. Since in this mode the control is performed ched through a cycle, then after determining the cycle length, it is necessary to switch to the clock ticker mode (2 - switch position 36 Length).

5 Thus, the proposed analyzer makes it possible to determine the presence of intermittent failure in pulsed sequences of large length in one measurement, to determine

At the time of occurrence of intermittent fault by changing the length of the monitored portion of the pulse sequence. At the same time, depending on the selected units

For the length of the pulse sequence, the location of the malfunction is determined step by step, for example, in the processor, first with the accuracy of the last transition, then with the accuracy of the command, and then with the accuracy of the SI. This shortens the search time for the first distorted symbol n of the pulse sequence.

Claims (1)

Invention Formula Signature analyzer for searching for interleaving fault faults, containing a group of counters, a group of decoders, a group of switches, a shift register, a counter, first to fourth triggers, first to third elements K, first to third elements OR, first to third display blocks and from the first to the third limit switches, where the information input of the first trigger is the information input of the analyzer, the overflow output of the i-th counter is connected to the counting input of the (1 + 1) -th counter, where, n, (n is the max. amount about bits for measuring the input sequence input spins), the outputs of the group counters are connected to the corresponding inputs of the group decoders and connected to the irpynne inputs of the second display unit, the outputs of the group decoders form a group of fixed contacts of the group switches, the moving contact i-ro switch is connected to the enable input (il) -ro group decoder, allowing the input of the n-th group decoder is connected to the bus of the logical unit of the analyzer, the reset inputs of the group counters are combined and connected to the output of the second the OR element, the first input of which is connected to the output of the second element AND, the first input of the first element AND is the first synchronization input of the analyzer, and the second input of the first element AND is connected to the direct output of the second trigger and the first inputs of the third element AND and the third display unit, the third element I is connected to the single input of the third trigger, the output of which is connected to the second input of the third display unit, the reset inputs of the counter, the third and fourth triggers are combined and connected to the moving contact v The first switch, the group of discharge outputs of the counter is connected to the group of inputs of the first display unit; the counter's first output is connected to the first input of the fifth element I, the second input and output of which are connected respectively to the moving contact of the first switch and the single input of the fourth trigger, right my and inverse outputs of which connected respectively to the third input of the third display unit and to the first input of the fourth element I, the second input of which is the input start of the analyzer, the output of the fourth element I is connected to the synchronous input of the second trigger, the reset input of which is connected to the third element OR, the first input of which is connected to the third contact of the third switch, the first and second fixed contacts of the first, second and third switches are respectively connected together and connected to the busses of logical zero and logical unit of the analyzer, respectively, characterized in that, in order to shorten the troubleshooting time, the analyzer contains a reg device modulo two., fourth display unit, control pulse shaping unit, comparison unit, first to third AND-OR elements and fourth and fifth switches, with the output of the first trigger connected to the adder modulo two, group the inputs of which are connected to the group of outputs of the shift register in accordance with nonzero coefficients of the constituent polynomial, the group of outputs of the shift register is connected to the group of information inputs of the register and the first group of information inputs of the comparison unit, ora group of which is connected to a group of information inputs about outputs of the register and a group of inputs of the fourth display unit, the output of the modulo two adder is connected to the information input of the sequential write of the shift register, the synchronized input of which is connected to the sync input of the first trigger, the output of the first AND-OR element and forms the sync output of the analyzer, the reset input of the shift register connected to the second input of the second OR element, and the output of the third AND-OR element, output second trigger is connected to the permissive input the second display unit, with the first inverse m input of the first OR element and with the start input of the control pulse shaping unit, the first and second outputs of which are connected respectively to the register input and the enable input of the comparator unit, the output of the comparator unit is connected to the counter input, the first input of the first I-IPI element is connected to the second input of the first AND element, the second input of the first element. the third and fourth inverse inputs of the first element I-1-SHI are combined and connected to the movable contact of the fourth switch, the fifth input of the first element AND-OR is connected to the high 10 the house of the first OR element and the first movable contact of the fifth switch, the fifth input of the second OR element is the analyzer Stop input, the output of the second AND-1SH element is connected to the second input of the third OR element, the output of the first OR element is connected to the information input of the second trigger whose inverse output and sync rotor are connected respectively to the first and second inputs of the third element AND-OR, the third and fourth inputs of the third element AND-OR the course of the first element And with the counting 15 are combined and connected to the rolling the input of the first counter of the group, the sub-contact of the first switch of the group is connected to the first input of the second element AND-OR and forms the sync output of the analyzer, the second input of the third element I is connected to the first input of the second element AND and the second input of the fourth element AND, the second input of the second element AND-OR the contact of the third switch, the direct output of the fourth trigger is the analyzer stop output, the first fixed contact of the fourth 20 switch is connected to the first non-impact contact of the first group and the third fixed contact of the second group of the fifth switch and is connected to the fourth inverse bus 25th, the second fixed contact of the fourth element AND-OR, with the second-right switch is connected to the second input of the second element AND and the third and third fixed the second contact of the second ne-first group and the first and second not, the switch, the third input of the second movable contacts of the second group of the I-YI element is connected to the sixth input 30p of the switch and connected to the second element AND-OR, second in the logical unit of the analyzer. Jjozl o Kb From 1G "Ji-g ki the house of the first OR element and the first movable contact of the fifth switch, the fifth input of the second OR element is the analyzer Stop input, the output of the second AND-1SH element is connected to the second input of the third OR element, the output of the first OR element is connected to the information input of the second trigger whose inverse output and synchronous input are connected respectively to the first and second inputs of the third AND-OR element, the third and fourth inputs of the third AND-OR element the third switch contact, the direct output of the fourth trigger is the analyzer stop output, the first fixed contact of the fourth switch is connected to the first non-idle contact of the first group and the third fixed contact of the second group of the fifth switch and the second fixed contact is even - the right switch is connected to the second and third fixed contacts of the first group and to the first and second fixed contacts of the second group of the fifth switch and n connected to bus analyzer logical unit. / C 5 th R phase P P PP PP P P P P P L, / P p p p l