SU1256228A1 - Device for detecting errors from elements of binary signal - Google Patents

Abstract

The invention relates to telecommunications. Error detection accuracy is improved. The device contains a synchronization unit 1, a sensor 2 control signals, a unit 3 of comparison, a trigger 4 states, a switch 5 signals, a shift register 6 (PC), an error signal generator 7 (FSO), a pulse counter 8 (SI), and sensor 9 of test signals and discrete channel 10, When a second impulse of noncomparison, detected by comparison unit 3, synchronization unit 1, appears during one cycle (L: 1

Description

A pulse is generated that cocks the 4 in 1 trigger, switching the switch 5 to the state of broadcasting noncomparison pulses to the clock input PC 6 stored in it. All non-comparison pulses emitted during cyclical failures

one

The invention relates to telecommunications and can be used to detect errors in binary signal elements during testing and routine checks of discrete communication channels.

The aim of the invention is to improve the accuracy of error detection.

Fig. 1 shows the structural electrical circuit of the device for detecting errors by the binary signal elements, Fig. 2 shows the structural electrical circuit of the synchronization unit.

A device for detecting errors by binary signal elements comprises a synchronization unit 1, a sensor 2 control signals, a unit 3. comparison, trigger 4 states, switch 5 signals, shift register 6, error signal generator 7, pulse counter 8.

FIG. 1 also shows the sensor 9 of the test signals and the discrete channel 10,

The synchronization unit 1 contains the shift register 11, the prohibition element 12, the unit synchronization element 13, the segment comparison unit 14, the 15th cycle phasing trigger, the 16 cycle mark generator, the pulse counter 17

A device for detecting errors in binary signal elements operates as follows.

The test signal from the cycle duration - (equal to 32767 elements) from the sensor output 9 test signals (figure 1) is fed to the input of the discrete channel Y. From the output of the discrete channel 10, the test signal goes to the information input of the synchronization unit 1 and, after passing through Register 11 (FIG. 2). passes

synchronization, the PC 6 output does not pass and does not distort the measurement result, which increases their accuracy. The goal is achieved by introducing trigger 4, switch 5, PC 6, FSO 7 and SI 8. An example of the execution of synchronization unit 1 is given. 2 Il.

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five

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on block 3 comparisons. In Comparison Unit 3, the received test signal is compared with the pilot signal from the sensor output of the 2 pilot signals.

The signal from the output of the discrete channel 10 is also fed to the element-by-element synchronization unit 13, which outputs the clock pulses, which, passing through the prohibition element 12, arrive at the clock input of the sensor 2 control signals. Element synchronization unit 13 ensures equality of speeds and coincidence of the fronts of the test and control signals arriving at comparison unit 3.

At the moments of cyclic synchronization activation or violation, the cycles of the test and control sequences will not coincide and it is necessary to phase them for the measurements, i.e. combine unambiguous elements of cycles. The criterion for the failure of frame alignment is the occurrence of a burst of incomparable pulses during one cycle, the magnitude of which is chosen equal to 22 pulses. The counting of noncomparison pulses, selected by comparison unit 3, is performed by counter 17, which is reset to the initial state by pulses from the generator output of 16 cycle marks. When a second pulse of incomparability appears during one cycle, at the output of the second bit of counter 17, which is the third output of synchronization unit 1, a pulse is generated that cocks trigger 4 into one, and the latter, in turn, switches switch 5 to the state of pulse transmission Incompatibility to the clock input register 6. In this case

pulses of incomparison arriving at the information input of register 6 are recorded into it, and since the width of register 6 is selected so that, before detecting a cycle alignment (filling with impregnation pulses of counter 17), its output pulses are not equal to TC, then all this time, the non-comparison pulses are stored in register 6. When the counter 17 is filled, the trigger 15 cyclic phasing is triggered, which gives a pulse to the input of the setting O of the register 6, while all the bits are zeroed. It also prohibits the issuing of clock pulses to the sensor 2 of the control signals, stopping its further operation, and the operation of the comparison unit 3, which stops the imbalance of the noncomparison, is prohibited. Thus, all noncomparison pulses extracted during frame synchronization failures at the output of register 6 do not pass and do not affect the measurement result, and therefore do not distort the measurement result, which increases their accuracy.

Due to the fact that in the pseudo-random sequence generated by the sensor 9 test signals and, accordingly, the sensor 2 control signals, the sequence segments do not repeat during the cycle, the segment coincidence in the register 11 with the sensor segment 2 control signals can occur only once in the cycle. At the moment of segment coincidence, the segment comparison unit 14 generates a pulse, which resets the cyclic phase trigger 15 to the initial state. In this case, it is allowed: the passage of clock pulses through the element 12 of the prohibition on the sensor 2 of control signals and the operation of unit 3 of comparison is allowed. The search for frame alignment ends there and the device goes into measurement mode to detect errors in the binary signal elements. In this case, the trigger 4 is reset to the initial state by the signal of the end of the cycle, generated by the generator 16 of the loop marks, and switches the switch 5 to the state of broadcasting clock pulses ha register 6. The latter transmits noncomparison pulses to

shaper 7 of the outbit signal, in which the gating is their gating clock pulses.

Counter 8, carried out the counting of clock pulses received at the input of the sensor 2 control signals fixes the number of bits of the received test signal.

Claims (1)

Invention Formula  A device for detecting errors in binary signal elements, comprising a synchronized synchronization unit, a pilot sensor and a comparison unit, the output of which is connected to the input of non-comparison pulses of the synchronization unit, whose information input is the input of the test signal of the device, that, in order to improve the accuracy of error detection, sequentially connected states of a trigger, a signal mutator, a shift register and an error signal generator, also a pulse counter, while the output of the comparison unit is connected to the first information input of the signal switcher and the information input of the shift register, the input Setting of which is connected to the first control output of the synchronization unit whose clock output is connected to the clock inputs of the pulse counter and signal conditioner error and to the second information-, dione input of the signal switch, the output of which is connected to the clock input of the shift register, and the output of the shift register is connected to the information one The error signal generator, the information and second control outputs of the synchronization unit are connected respectively to the second information and control inputs of the comparison unit, the third and fourth control outputs of the synchronization unit are connected respectively to the inputs Set to 1 and Set to O of the state trigger, the output of which connected to the control input of the signal switch, and the auxiliary output of the sensor of the control signals is connected to the additional information input of the syncro unit 51256228 ning, with the outputs of the pulses being respectively the l of the error signal and the counter im first and second outputs of the device, FIG. g Editor V. Ivanova Compiled by V. Orlov Tehred I.Popovich Proofreader O. Lugova Order 4837/58 Circulation 624 Subscription . VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4