SU1487066A1 - Device for computing sliding mean - Google Patents

Description

The invention relates to computing. The aim of the invention is to improve the accuracy of the device, the Device contains a generator 1 clock pulsesblock 2 formation of pulses, reversible counter 3, block 4 memory, the first 5 and second 6 address counters, block 7 comparison, buffer register 8, address switch 9, block 10 elements NOT the switch 11, the adder 12, the first 13 and the second 14 registers. 2 Il.

2

1487066 A1

Sri & L

1487066

four

The invention relates to computing and can be used to determine the moving average in digital information processing devices, digital measuring devices and other devices.

The purpose of the invention is to improve the accuracy of the device.

Fig, 1 shows the functional diagram of the device for calculating the moving average; figure 2 - diagram of the unit of formation of pulses

The device 1 comprises a clock generator, the formation .blok 2 ¹ Bani pulses, a reversible counter 3, a memory unit 4, the first 5 and second 6 counters address comparing unit 7, the buffer register 8, a switch 9, the address, the block elements 10 do not, the switch 11, the adder 12, as well as the first 13 and second 14 registers.

Block 2 of the formation of pulses includes three три-trigger 1 5 15 _} , four elements AND 16 ^ -16 ^, the fifth element AND-NOT 17, first to fourth elements AND-NOT 17 _g -17 ₅ , the second, third and first elements NOT 18, -18 ^ respectively.

The device works as follows.

When information arrives at the device input, a trigger 15 $ of a block 2 for forming pulses on the leading edge of a clock pulse that accompanies the information goes into one state, allowing the passage of clock pulses with frequency E. from generator 1 through element I16 ^ to the divider, frequencies on triggers 15, and 15 ^. Pulses of E, E / 2, E / 4 frequency are fed to elements AND 16 ^ —16 * and NOT-17. The outputs of which are the signals “Sampling resolution C8”, “Recording resolution IE”, “Summing” Σ, “Clock pulse” "TI and" Reset "SB, Signals EI and TI arrive at the elements AND-NOT 17 U17 ₅ , which are commutators of the type of work; block" Write-read ", they are controlled by the signal A? Ν, where A is the volume of received informationN is the volume of a given sample.

The signal Α> Ν comes from block 7 comparison. The signal records the result of the summation from the output of the adder 12 into the register 13 of the device. SAT signal after forming

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thirty

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45

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All signals return unit 2 of the formation of pulses to its original state.

In the initial state, the device is in the "Record" mode, since the reversible counter is in the zero state, i.e. Α ^ Ν and the signal Α> Ν is not generated. Address address to RAM is determined by the state of the counter 5 address. After the information arrives at the device input, the pulse shaping unit generates signals C8 and IE on the RAM. In memory block 4, the received information code is recorded, at the same time this information code through the switch 11 enters the adder 12 and when the clock signal arrives, it is recorded in the register 13. Then from the pulse shaping unit 2, the clock pulses + TI arrive at the address counter 5 and the reversible counter input, the address counter 5 changes the address of the record, and a one is written into the reversible counter. In addition, the pulses + TI overwrites the code of a given sample size N in the buffer register. With the arrival of the next information code, the device repeats the "Record" cycle. In the reverse (the counter counts the number of codes of the received information A. In the "Record" mode, the device works until the received information A exceeds the number; the specified sample size is N. After as the code at the output of the reversible counter becomes equal to the specified sample size Ν, the output Р Equal ’of the comparison block 7 is a signal = перед, the leading edge of this signal overwrites the information, the result of summing N received codes, from the register and 13 to register 14.

After writing (Ν + 1) -γο code values, the content of the reversible counter becomes + 1 and the signal сигнал> Ν appears at the "More" output of comparison block 7. This signal translates the pulse shaping unit 2, the address switch and the switch 11 into the “Read” mode, the address of the access to block 4 is determined by the state of the address counter 6, the information read from the memory block 4 through the block 10 elements NOT and the switch 11 as a return code arrives at the input of the adder, So about1487066

at once, the subtraction operation is performed. In the readout mode, Tj is fed to the counter 6 of the address and to the input of the subtraction of the reversible counter, the value in the reverse counter decreases by one and becomes Α = Ν.

At the output of block 7 of comparison, the signal Α = сним appears and the signal Α> Ν is taken. The pulse shaping unit, the address switch and the switch 11 are returned to the initial state (to the "Record" mode). With the arrival of the next information code at a constant volume of a given sample N, the "Record-read" cycle (summation and reading) is repeated.

If the code of the specified sample size has been changed upwards: Ν (> Ν μ, where N is the code of the previous sample size; Ν | is the new code. Of the sample size, the device will work only in the Record mode (summation) until the contents of the reversible counter A does not become equal to т.е., i.e. before the appearance of the signal Α = Ν from the output of the comparison block 7, then the device switches to the "Write-read" mode,

If the specified sample size has changed in the direction of reduction, that is, Ν ^ то μ, then the device will work as follows. With the arrival of the information code, the received code is recorded and summed, and the value of the sample volume code Ν is written to the buffer register _; , the contents of the reversible counter becomes Α = Ν,., + 1, i.e.,

And more Ν | by 4Ν + 1, where dT1 =

= Νμ, - Ν | at the same time, the new value of the sample size code is recorded in the buffer register, at the output of comparison block 7 a signal сигнал? Ν appears and the device switches to the "Read" (subtraction) mode. After performing ΔΝ + 1 operations "Reading" (subtraction) at the addresses determined by the second counter 6 of the address, the content of the reversible counter becomes ^! equal to Ν ·, the output of the comparator produces a signal Α = Ν, the sum of N · codes of the received information is recorded in the second register, that is, the current value of the moving average, and simultaneously with the appearance of the signal Α = Ν, the output of the comparator 7 is removed ? Ν and the device goes to its original state (in

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"Record") and is awaiting the next information code.

The period of the "Write" cycle (summation) is determined by the frequency of arrival of the code information, the period of the "Read" (subtraction) cycle is determined by the clock frequency of the generator. The ratio of these frequencies is determined by the maximum possible change in the code that determines the sample size:

Jaap

2) t.

COUNT ”

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thirty

1-1

O = ΙΝΤ (“-) - 2;

• lacquer + count

ΙΝΤ is the integer part of a number.

The device operation algorithm is described by the following formulas:

, with Ν ^ Νμ, ί 4Ν; -Νμ _Τ Ν. ;

25 where y (s.), Y (b,) are the values of the output code of the device, respectively, at times and t;

х (Г) is the value of the input code at the moment С _{ ;

- the previous code value of the sample size;

- the current value of the sample code,

Y (C {) - Y (^. ₍ ) ⁺

at Ν ₄ > Νμ ,; ίΝί I r N

⁴⁰ where is the moment of time following the moment of changing the sample size code;

ί = s + ΔΝ

₄₅ if s = 1, then y (r _s ) = o,

Claims (1)

Claim 35 A device for calculating the moving average containing a memory block whose information output is NOT connected to the first information input of the switch through the block of elements, the second information input 55 of which is combined with the information input of the memory block and is the information input of the device, the switch output is connected to the first information input of the adder , exit to · 1487066 Secondly, it is connected to the information input of the first register, the output of which is connected to the second information input of the adder, and to the information input of the second register, whose output is the output of the device, clock generator, the first address counter, characterized in that A second address counter, a comparison unit, a buffer register, an address switch, a reversible counter and a pulse shaping unit, consisting of three NOT elements, four AND elements, three три-flip-flops and five e, are entered I-NOT elements, while the outputs of the first and second address counters are connected respectively to the first and second information inputs of the address switch, the output of which is connected to the address input of the memory block, the inputs of the sampling resolution and recording resolution of which are connected respectively to the outputs of the first and second I elements -NO, the output of the third element is NOT connected to the counting input of the first address counter, to the summing input of the reversible counter and to the clock input of the buffer register, the output of which is connected to the first information On the on-line input of the comparator, the second information input of which is connected to the output of the reversible counter, the input of which is subtracted with the counting input of the second address counter and connected to the output of the fourth H-NOT element, the clock input of the first register is combined with the first input of the second AND element and connected to the output of the second element And, the clock input of the second register is connected to the output "Equal" of the comparison unit, the output "More" of which is connected to the control inputs of the switch, the address switch, to the input of the first element NOT the first input of the third element N-NOT, the second input of which is combined with the first input of the fourth element NAND and connected to the output of the third element AND, the output of the fourth element AND connected to the first input of the fifth element NAND and to the input of the element NO, the output of which is connected with the K-inputs of the first and second P-flip-flops, the output of the first element And is connected to the C-input of the first ϋ-trigger, to the first input of the third element And and through the third element NOT to the first inputs of the second and fourth elements And, the second inputs of the third and Thursday of the correct item and volume dinene with 13-input second три-flip-flop and connected to the inverse output of the second ϋ-flip-flop, C-input of which is connected to the direct output of the first ϋ-flip-flop, the inverse output of which is connected to the first ϋ-flip-flop “with the second the input of the second element is And,, with the first input of the first element AND-NOT, the second input of which is connected to the direct output of the second три-flip-flop, the output of the first element НЁ is connected to the second inputs of the second, fourth and fifth elements AND-NOT whose output is connected to K -input the third trigger, C — whose input is connected to the output of the clock generator, the direct output of the third три-trigger is connected to the first input of the first element And, the second input of which is the synchronization input of the device. 1487066 ν-ν (ri & 2