SU1485232A1 - Divider - Google Patents

Description

The invention relates to computing and can be used in arithmetic devices operating in Fibonacci codes for dividing numbers in half. The purpose of the invention is to increase speed. The device contains the register I of the dividend, the counter 2 modulo <two, the control block 3, the register 4 half-weights of the Fibonacci 1-code, the adder 5, the register 6 private, the information input 7 of the device 7, the input 8 of the initial installation of the device , input 9 of the device constant, output 10 of the device. The division of numbers in the Fibonacci 1-code in half in half the time, two times smaller than in the known device for division.

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The invention relates to computing and can be used in arithmetic devices operating in Fibonacci codes for dividing numbers in half.

The aim of the invention is to increase speed.

FIG. 1 shows a diagram of a device for dividing; in fig. 2 - control unit diagram.

The device contains (Fig. 1) divisible register 1 for storing and shifting two digits in the direction of the higher digits of the 1-code / Fibonacci divisible, counter 2 modulo two, which generates the correction code of the private code, control unit 3, register 4 half of the 1-Fibonacci weights, designed to form, by shifting towards the lower digits, a sequence of half-weights of the онач-Fibonacci code, adder 5 and register 6 private, information input 7, from which divisible code is entered into register I of the dividend, input 8 is initial of the installation from which the signal is written to the register 1 of the dividend and the register 4 is the half of the weights of the 1 Fibonacci code, input 9 is constant, output 10, inputs 11 and 12 of control unit 3, and outputs 13-16 of control unit 3.

The control unit 3 (FIG. 2) contains a table analysis node 17 and triggers 18 and 19.

The coding table analysis node 17 is given in table. one.

In the η-bit 1 Fibonacci code, a number A is represented in

. the form

A = a _n „, cf, (n-1) + ... + A _o c> ₍ (0), where a - £ ^ 0, C is a binary digit in ΐ-m

code discharge;

(ί) - the weight of the ΐ-go of the digit code, equal to the ΐ-th Fibonacci number.

A number equal to half A can be written as follows:

then, when dividing a Fibonacci code in half, the private code will be obtained by summing the codes of the half weights of the Ι-kbda Fibonacci unit digits. The weight of each digit T.-code

Fibonacci code for the integer part of its half is assigned.

In tab. 2 shows half codes

R

the weights of the nine first digits of 1-ksch Fibonacci. The code of half the weight of the ίth digit is obtained by shifting by ϊ digits towards the lower digits of the code of half zero (senior) digit.

To obtain an error of a result not exceeding one, it is necessary to add a correction code to the code of a particular one obtained as a result of adding the codes of half weights of unit digits of the dividend. The magnitude of the correction is equal to the integer part of half the number of single digits c. odd weights of 1-Fibonacci divisible code. The result correction can be entered both at the end of the division operation and in it. process. In the proposed device uses the second method. Thus, the quotient of dividing a number in a Fibonacci 1-code by two is

to

5 = ΣΖ a; B; + F,

ί = 0

where is a; - binary digit in the ΐth digit of the code of the dividend;

Βό is the code of half the weight of the ίth digit;

¢ 1 - correction code.

When dividing in half, the analysis of the digits of the 1-Fibonacci code of the dividend begins with the higher digits, and since the dividend is represented in minimal form, it is analyzed in two digits, considering three possible cases: "00", "01", "10".

The device (Fig. 1) works as follows.

The signal input to the device 8 is used to write into register 1 of the dividend divisible code that arrives at device information input 7, and to register 4, the half weight code of the high-order bit of the 1 Fibonacci bit grid used, which arrives at the information input of register 4 Input 9 device.

Each cycle of operation of the device begins with the analysis of the two most significant bits of the register I of the dividend, arriving at the inputs of the control unit 3. As a result of the analysis formed up52

6

⁵ 10852

driving signals that determine the sequence of actions in the device in the current cycle.

If the values of two analyzed digits of the dividend are equal to "10", then ⁵

the register of the half of the weights of the bits of the 1 Fibonacci code and the private register 6 in the adder 5 is summed, the result is recorded, the θ is written into the private register 6, then the contents of the register 1 of the dividend are shifted by two bits to the high bits, half of the weights of the bits of the 1-code Fi- 15 baconci code — two digits in the direction of the lower digits, and the next work cycle begins. If the values of the two analyzed digits "01", then there is a shift by one digit in ₂ 0

the side of the lower bits of the register contents 4 codes of the half weights of the bits of the 1 Fibonacci code, then in the adder the contents of ¹ registers 4 and 6 are added. After this, the 25 bits of the register 4 are shifted to the low bits of the register 4 and two bits are shifted to the side senior bits of the contents of the register 1. The next clock cycle begins. If the contents of the analyzed bits of the dividend "00", then in the current clock cycle there is a shift by two bits from the contents of register 1 towards the high bits and the contents of register 4 towards the low bits. In each step of the device! when summing up the registers' 4 and 6 on the adder, the value of the lower digit of register 4 is fed to the counting input of counter 2,,

which, using the control signal received at the resolution input, calculates the number of summable half scales of 1-bit Fibonacci bits

chi containing "1" in the low order.

This indicates that the discharge-1-Fibonacci code of the dividend from the pair of digits considered at this stage, containing "1", has an odd value of weight. When the value of counter 2 becomes equal to two, then in the same work cycle, "1" is applied to the transfer input of adder 5, pos35

what is it that counter 2 is reset. The signal of the end of the division operation is the equality to zero of the contents of register 1.

The description of the operation of the device shows that the maximum number is 55

The combo for which the operation of dividing a Fibonacci 1-code in half is performed is equal to the maximum possible number of units in a Fibonacci 1-code of digit length. Considering the minimal form of representing numbers in a 1-Fibonacci code, the maximum number of device operation cycles is n / 2. An additional positive effect of the invention is to reduce hardware costs.

Claims (1)

Claim 1. A device for dividing, containing the register of the dividend, the control unit, the register of the weights of the 1 Fibonacci code, the adder and the register of the private, the information input of the device connected to the information input of the register of the dividend, the input resolution of which is combined with the input resolution of receiving the register of the half weights The 1 Fibonacci code is the input of the initial setup, the input of the constant of which is connected to the information input of the register of half weights of the 1 Fibonacci code, the output of the adder is connected to the information input of the register The output of which is connected to the input of the first term of the adder, characterized in that, in order to improve performance, it contains a counter modulo two, and the outputs of the two most significant bits of the register of the dividend are connected respectively to the first and second inputs of the control unit, the first, second, third "and the fourth outputs of which are connected respectively to the input of the resolution of the shift by two digits in the direction of the upper digits of the register divisible, with the inputs of the resolution of the shift by one digit and two digits in the direction of the lower digits of the half Weights of the 1 Fibonacci code, with the input of the private register receive permission, the output of which is the device output, the low-order bit output and the register of the half-weights of the Fibonacci 1-code, are connected respectively to the counting input of the modulo-two counter and the input of the second adder which is connected to the output of the modulo two counter, the input of the permission of which is connected to the fourth output of the control unit. 2. The device according to p. ^ Characterized in that the block pack 7 ! 085232 eight the alignment contains a table analysis node and two triggers, the first and second inputs of the control unit being the corresponding inputs of the table analysis node, the first to fourth outputs of which are the corresponding outputs of the block control, the second and fourth outputs of the tabular analysis node are connected respectively to the inputs of the first and second triggers, the outputs of which are connected respectively to the third and fourth inputs of the tabular analysis node. Table I eleven 12 18 ----- ¹³ Γϊγ- ¹⁵ 0 0 X X one 0 one 0 0 one X 0 0 0 0 one 0 one X one one 0 one 0 one about 0 0 0 one 0 0 one 0 one 0 0 0 0 one one 0 0 one one one 0 0 Table 2> Discharge Weight Half weight code 4, (ί) <ρ, (ί) 2 21 13 eight five 3 2 one one 0 55 27 one 0 0 one 0 0 one 0 one 34 1.7 0 one 0 0 one 0 0 one 2 21 ten 0 0 one 0 0 one 0 0 3 13 . 6 0 0 0 one 0 0 one 0 four eight - four 0 0 0 0 one 0 0 one five five 2 0 0 0 0 0 . one 0 0 6 3 one 0 0 0 0 0 0 one 0 7 2 one 0 0 0 0 0 0 0 one eight one 0 0 0 0 0 Ό 0 0 0