SU1478366A1 - Pseudorandom signal data transmitter - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the speed of information transfer. The device for transmitting information contains r-1 clock pulses, element 2, blocks 3 and 6 of setting the initial state, counter 4 pulses, element 5, shift register 7, adders 8 and 9 modulo two, decoder 10 and switch 11, consisting of elements OR 12,13,14 and 15 and elements AND 16,17,18 and 19. The operation of the device consists of three stages. The first stage includes a set of pseudo-random sequence (PSP) cutoff length using the setup block 3, the cipher suite of the message being generated using the setup block 6, supplying control signals to the inputs of the decoder 10 to form register 7 feedbacks in accordance with the selected untranslatable polynomial. The second stage involves recording the length of the PSP cutoff set in block 3 to counter 4, recording the cipher of the generated message to register 7. The third stage involves transmitting information. The goal is achieved by the introduction of the installation units 3 and 6, the adder 9 and the switch 11. The device according to claim 2 f-ly is characterized by the execution of the switch 11. 1 Cp. f-ly, 1 ill.

Description

V vj

About ©

oh

WITH&

about

The invention relates to telecommunications and can be used in discrete information transmission systems using pseudo-random signals.

The purpose of the invention is to increase the speed of information transfer.

The drawing shows a structural electrical circuit of a device for transmitting information by pseudo-random signals.

The device contains a generator 1 clock pulses, the element And 2, the first block 3 setting the initial state, the counter 4 pulses, the element OR 5, the second block 6 setting the initial state, the shift register 7, the adder 8 modulo two, the additional adder 9 modulo two, a decoder 10 and a switch 11.

Switch 11 contains the first - the fourth elements OR 12-15 and the first - the fourth elements And 16-19.

The device for transmitting information by pseudo-random signals works as follows.

The first stage (preparation for work) includes a set of pseudorandom sequence cutoff length (PSP) using the first block 3 settings, a set of cipher (number) of the generated message using the second block

6 settings, supplying control signals to the inputs of the decoder 10 to form register feedbacks

7 in accordance with the selected untranslatable polynomial. The second stage involves recording the length of the PSP cut-off set in the first block 3 into the counter 4, recording the cipher (number) of the message being generated to the register 7. The third stage is the transfer of information.

Depending on the required length of the PSP section in the first installation unit 3 (the PSP cut-off length selection unit), the number of elementary signals (bits) of the formed PSP is set in binary code. Information from the first installation unit 3 is supplied to the installation inputs of the counter 4.

Writing a number in a binary code is carried out when a pulse is applied. Recording to the clock input of the counter 4. In the second installation block 6, the number of the generated message is set in the binary code, recorded in register 7 after it is fed

Pulse Record on the recording input.

After starting the generator 1, it starts generating a sequence of clock pulses that are sent to the element 2. After writing to the counter 4 a binary code combination at its corresponding outputs

Q potential signals 1 appear, which arrive at the element OR 5. At its output also. Signal 1, which arrives at the AND 2 element, allows the passage of clock signals.

pulses to the subtracting input of the counter 4 and to the clock input of the register 7 until the output of the counter 4 does not receive the signals O, as a result of which

0 signals O at the output of the element OR 5 and at the second input of the element I 2, prohibiting the passage of pulses through it.

Therefore, the number of elementary

5 signals in the generated memory bandwidth (length

cutoff) is uniquely determined by the binary number that is installed on the setting inputs of counter 4 using the first unit 3 of the installation.

0 The initial conditions for the operation of register 7 are set by the second unit 6 of the installation. Register 7 shifts the cipher of the message that is written in it at times determined by incoming pulses from the output of element 2 to its clock input. In the first adder 8, modulo two information recorded in register 7 cells occurs.

0 The selection of a given sequence occurs by setting in binary code the sequence number at the inputs of the decoder 10. In this case, one of the outputs of the decoder 10 appears

5 potential signal 1, which goes to the first - fourth elements OR 12-15 of the switch 11. From the outputs of the first - fourth elements OR 12-15, the signal goes to the first - fourth elements AND 16-19 of the switch 11, thereby ensuring the connection of the corresponding register cells 7 to the adder 8.

Modulo-summed two message elements (corresponding to the state of register 7 cells) from the output of adder 8 are fed to register 7, ensuring the formation of a given memory bandwidth.

0

five

At the output of the additional adder 9, during delivery of the clock pulses from the generator 1 through the element AND 2, a bandwidth of a given length is formed, which enters the communication channel. If a potential signal 1 is fed to the second input of the adder 9, then the inverse of the memory bandwidth is formed at its output.

Claims (2)

1. A device for transmitting information by pseudo-random signals, containing serially connected clock pulses, an AND element, a shift register and a modulo-two adder, the output of which is connected to the information input of the sequential shift register, as well as a pulse counter, a decoder, and an OR element, the input of the clock generator and the inputs of the decoder are respectively the trigger input and information inputs of the device, characterized in that, in order to increase the transmission speed A switch, the additional modulo two and the first and second blocks of the initial state setting are entered, while the outputs of the first block of the initial state are connected to the corresponding setting inputs of the pulse counter, the subtracting input of which is connected to the output of the And element, to the second input the output of the element OR is connected, the inputs of which are connected to the corresponding outputs of the pulse counter, the outputs of the second setup unit of the initial state are connected to the corresponding settings m inputs of the shift register, the additional outputs of which are connected through the switch 0 0 5 d 5 0 five to the corresponding inputs of the modulo-two adder, the control inputs of the switch are connected to the corresponding outputs of the decoder, and the first input of the additional modulo-two adder is connected to the output of the shift register, the clock input of the pulse counter and the pulse counter and the second input of the additional modulo two are clock and control inputs and auxiliary information input respectively. devices i 2. Device pop. 1, characterized in that the switch comprises the first, second, third and fourth OR elements, the outputs of which are connected respectively to the first inputs of the first, second, third i fourth AND elements, the first input of the first OR element connected to the first inputs of the second and third elements OR, the second input of the first element OR is connected to the second input of the second element OR, and to the first input of the fourth element OR, the third input of the first element OR is connected to the second inputs of the third and fourth elements OR, third the input of the second element OR is connected to the third inputs of the third and fourth elements OR, the first, second and third inputs of the first element OR, the third and fourth inputs of the second OR element and the fourth input of the third OR element are the control inputs of the switch, the second inputs and outputs of the first - the first, second, third and fourth elements And are respectively the information inputs and outputs of the switch.