SU1427589A1 - Discrete information receiver - Google Patents

Description

The invention relates to radio technology and can be used in radio receivers having several modes of receiving discrete information,.

The goal of the enhancement is to increase the speed of the device by reducing the search time for the optimal operation mode.

Fig. 1 shows the structural electrical circuit of the device proposed; Fig. 2 shows the stress plots explaining his work.

A device for receiving discrete information contains a radio receiver 1, a generator of 2 rectangular pulses, the first element AND 3, the inverter 4, the second element AND 5, the first shift register b, the first and the second differentiating unit 1 and 8, the second register 9, the first depfractor 10, the first and second formers 11 and 12 rectangular pulses, the second decoder 13, the first memory block 14, the OR 15 element, the second memory block 16, the third decoder 17, and the mode switching block 18.

The device works as follows.

The radio receiver 1, according to the signal from block 18, receives an information signal consisting of a combination of single, binary and other pulses. In order to establish the optimum operating mode of the radio receiver 1, information from its output (first single entry) (FIG. 2 a) goes to the first input of the second element 5, the first differentiating unit 7 and the inverter 4, and from the generator 2 square-wave pulses in parallel The second inputs of the first and second elements I. 3 and 5 receive clock signals (Fig. 2c), which through the second element 5 arrive at the counting input of the second shift register 9 and from its output to the input of the third decoder 17 (Fig 2d) where, the length of the information parcel (number have zeros and ones) is determined by the operating mode. In addition, the first unit through the inverter 4 is fed to the first input of the first element 3, to the second input of which a pulse sequence is received from the generator 2 square-wave pulses, because the information is inverted, the clock pulses to the first shift register 6 are not received in the second decoder 13

0

five

0

five

0

five

0

five

0

five

a sequence of zeros is written. At the same time, on the leading edge of the first information parcel, the first differentiating unit 7 interrupts a short pulse (Fig. 2e), which is converted by the first shaper 11 rectangular pulses into a 1 rectangular pulse (Fig. 2h) and enters the read input of the second decoder 13 and through the element OR 15 - to the reading input of the first decoder 10. According to this impulse, information is retrieved from the second decoder. 13, writing it to the first memory block 14 and transiting to the second input of the first decoder 10. Since the combination of zeros is fed to the input of the first decoder 10, there will be a combination of zeros at its output and mode switching does not occur.

Upon receipt of the zero dressing (Fig. 2a), it is inverted in inverter 4, after which it is fed to the first input of the first element I3 (Fig. 26), to the second input of which clock signals are received from the generator 2 of rectangular pulses. The clock signals are sent to the counting input of the first register 6 of the shift and from it to the input of the second decoder 13 (Fig. 2d), where the operating mode is also determined from the information package (zero). At the same time, the second differentiating unit 8 generates a short impulse (Fig. 2g) on the leading front of the inverted package. 15 - to the matching input of the first decoder 10. The code combination (Fig. 2d), corresponding to a certain number of zeros and ones, from the output of the third decoder 17 enters the input of the rya memory block 16 and transits - and the first input is p First decoder 10.

When the third information parcel (unit) arrives, the code combination is read from the second decoder 13, the analysis of two code combinations from the third and second de. encoders 17 and 13, respectively. Determining the optimal operation mode is performed according to the following rule:

1. All modes of operation are normalized relative to the mode with the highest transmission rate, i.e. with the smallest duration of an elementary parcel T. For example, for a 2AOO rate, Bod is mode A. Thus, Td T; T

, 2T b

to make a false decision, i.e. redundancy reduction (in particular, in terms of search time) is at the expense of reliability; the proposed device uses the method of deterministic analysis, i.e. a priori information is taken into account on possible modes of operation, on the possible multiplicity of informations AT; Tr 48T | (Table 1). | o zationnyh parcels and possible common

2. The multiplicity of the unipolar pulse (information dressing) in the code combination may be different. For example, the maximal multiplicity of K is equal to 5: K, 1, K ,, ... (tab. Y.

3. Dp each mode of operation, the duration of the information package is determined by the expression:

featured. From all this information two groups are selected, the normalized data of characteristic differences and common features, i.e. that information

15 in which it can be said with a probability equal to one that the given duration of the information parcel corresponds to S modes from R possible, where, and the next parcel

T.- K

T „-. TO:

A 1 6-4

as shown

TC-K

l

20 corresponds to X modes from R possible, where, moreover for X and

in tab. 2, from where

it follows that the ambiguity in determining the mode of operation appears due to the absence of differences between a single sending of a Viv mode, a binary sending — 25 days is equal to 0.99, and for four - 1. a mode A, etc.

Thus, there are two groups: an unambiguous definition of the mode by the pulse duration and an 11-digit definition (Table 2),

4. In the first and second registers

S There can be only one mode of operation, with probability 91. The accuracy of determining the mode of three

Claims (2)

Invention Formula Device for receiving discrete rear information containing a generator rectangular pulses, the first element And, the first decoder, the outputs of which are connected to the inputs through the mode switching terminal the shift uses the outputs of only those cells that correspond to the numbers table. 2. In accordance with this 9 to make a false decision, i.e. redundancy reduction (in particular, in terms of search time) is at the expense of reliability. The proposed device uses a method of deterministic analysis, i.e. A priori information about possible modes of operation, possible multiplicity of information packages and possible general parcels and possible common featured. From all this information two groups are selected, the normalized data of characteristic differences and common features, i.e. that information where it is possible to say with a probability equal to one that the given duration of the information parcel corresponds to S modes from R possible, where, and the next parcel corresponds to X modes of R possible, where, moreover, for X and the equivalent is 0.99, and four is S There can be only one mode of operation, with probability 91. The accuracy of determining the mode of three Invention Formula An apparatus for receiving discrete information comprising a generator rectangular pulses, the first element And, the first decoder, the outputs of which are connected to the inputs through the mode switching terminal from the outputs of the third and second controllers, the output of which is connected to the input Tori 17 and 13 to the input of the first decoder 10 receives a code combination corresponding to a particular mode in accordance with the table. 3 5. The first decoder 10 compares 40 code combinations of modes and determines the operation mode according to the rule: if A, then A; if B, then B; If F, then F. If from the third decoder 17 - AB, the ac of the second decoder 13 - Sun, then definitely - mode B. Since the determination of the optimal mode of operation in most cases is made on the basis of the minimum information message, the probability of occurrence of which in a certain interval should be equal to one, as a rule, very large redundancy is introduced. There are many ways to reduce this redundancy, but all of them are associated with a certain percentage of the risinvertor, the OR element, two shift registers and two memory blocks, distinguished by the fact that, in order to improve the performance of the device by reducing the search time for optimal operation, the second and the third decoder, two differentiating units, two square pulse formers to the second element, And, the first input of which is connected to the input of the inverter, the output of which is connected to the first input of the first element, And, and from the input the first differentiating unit, the output of which is connected to the first input of the element OR, whose output is connected to the control input of the first decoder, and to the control input of the second decoder, to the control input of the first decoder, and to the control input of the second decoder respectively, with the outputs of the first shift register, to the information 50 55 ka, the output of which is connected to the input an inverter, an OR element, two shift registers and two memory blocks. Distinguished by the fact that, in order to improve the speed of the device by shortening the search for the optimal mode of operation, the second and third decoders, two differentiating blocks, two formers of rectangular pulses are introduced to the second the element And, the first input of which is connected to the input of the inverter, the output of which is connected to the first input of the first element And, and to the input of the first differentiating unit, the output of which through the first shaper s is connected to the first input of the OR gate, whose output is connected to the control input of the first decoder and to a control input of the second decoder, information, input, output and control data outputs of which are connected respectively to the first shift register outputs to the information 51427589 the input of which is connected to the output is connected to the output of the second shaping element I, with the installation input of rectangular pulses, with the house of the first shift register and with the input installation input and outputs with the inputs of the first memory block, the outputs are co- (. of the shift register, to the information one are connected to one information input of which the output is connected: the input inputs of the first decoder, the second element I, the second input which other information inputs of which are connected to the output of the generator are connected to the outputs of the second block of the second memory, the first information outputs of the third decryption input of which is connected to the input of the second, the control input, the control differentiating unit, the output output and the information inputs which is connected to the input of the second jcOToporo are connected respectively to the rectangular pulse shaper by the second input of the OR element, to which 15 are. .I Table 1 Table 3 Continued, .tab l. 3 de n . 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