SU1418698A1 - Number sorting device - Google Patents

Abstract

The invention relates to automation and computing and can be used in data processing devices. The purpose of the invention is to improve speed. The device contains a shift register 1, three triggers 3, 2, 9, delay element 5, three elements AND 4, 6, 8 and element R1PI 7. The proposed device receives binary sequences and controls their length. In the case of the correct length of the received binary sequence, it can be output to some processing device. In the case of a kopOTKoro message, the device ends up after receiving the sign of the end of the message, and in the case of a long message, after receiving the number of bits equal to the required one. 1 il.

Description

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Ke and computer technology and can dig used in data processing devices.

The aim of the invention is to increase speed.

The drawing shows a diagram of the device.

; The device contains a register of 1dvig, triggers 2 and 3, element 4, element 5 delay, element 6, element OR 7, element IV, trigger 9, initial installation stroke 10, input 11 for end of message, information input 12, clock input 13, message permission output, informational output 15, and message disabling output 116.

Received message of the required length. At the same time, according to the nth clock pulse at input 13, the unit, initially recorded in the first register bit 1, arrives at the direct input of trigger 3 and sets it to the unit state. The incoming input device 11 sign of end

the message triggers element 4, from the output of which the signal goes to the direct input of trigger 2 and sets it to one. At output 14, the message output of the device appears high. On pulses at input 13, a message from output 15 of the device can be received by some processing device. For

The device is designed to control the prevention of the element's response to the length of the message received by the I register by a sequential code. I The device works as follows.

I Before receiving the message, the device I in the pulse from input 10 is set to its initial state. When this I triggers 2, 3 and 9 are zeroed, all I bits of register 1, except for the first, I also zeroed, and the first bit: register 1 is set to 1; condition. After that, at the entrance; 13, a series of clock pulses is applied. I For each clock pulse, the contents of register 1 are shifted by one bit towards the last bit, after which the next bit of the message is fed to input 12 and is written to the first bit of register 1. After the last bit of the message arrives, a sign is output the end of the message on the input 11 of the device.

When receiving a message on register 1

The following situations may occur.

I

The received message is shorter than required. In this case, the unit 1 initially recorded in the first register bit does not have time to move out of it and set trigger 3 to one state, so when the input of device 11 arrives at the sign of the end of message AND 8, the output from which OR 7 signal goes arrives at the direct input of the trigger 9. At the output 16 of the prohibition of issuing messages to the device, a high level appears.

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mA 6 the delay time of element 5 must not be less than the time of setting trigger one in one state. Trigger 2 installed in one state low from the inverse output closes element 6. And the received message is longer than required. In this case, according to the nth clock pulse at input 13, the unit 1 initially recorded in the first register bit is fed to the direct input of trigger 3 and sets it to the unit state. Since trigger 2 is in the zero state, then through the delay time of element 5, the next clock pulse at input 13 triggers element AND 6, from which the pulse passes through the element OR 7 and sets trigger 9 to one state. Output 16 prohibits the issuance of device messages to appear high.

After the message is issued, in the case of its correct length, or after the potential at the output of the prohibition of issuing messages to the device input 10 is detected, the impulse is returned again. The device is ready to receive the next message. In the case of receiving a long message, the high level from trigger 9 should go to the device from the output of which the message goes to this device and stop issuing the message.

Claims (1)

5 claims A device for sorting numbers containing the shift register, the first and second triggers, and the first element 0 five a delay element, the input of the initial installation of the device is connected to the inputs of the installation of the first and second triggers and the shift register, the first bit input of which is the information input of the device, the shift input is connected to the clock input of the device, and the high bit output of the shift register is an information output of the device and connected to the installation input to the one state of the first trigger, the direct output of which is connected to the first input of the first element AND, the second input of which is the input of the end of the message device, and the output is connected to the installation input to the single state of the second trigger, the output of which is the output of the resolution permitting the device to issue a message, which, in order to increase eight speed, the second and third elements AND, the OR element and the third trigger are entered into it, the clock input of the device is connected to the first input of the second AND element, the second input of which is connected to the inverse output of the second trigger, and the third input through the delay element the first trigger, the inverse output of which is connected to the first input of the third element And, the second input of which is connected to the clock input of the device, the outputs of the second and third elements AND are connected to the inputs of the OR element, the output of which is connected to the input of the installation in the single state of the third trigger, the installation input in O which is connected to the input of the initial installation of the device, and the direct output is the output prohibiting the issuance of messages from the device.