SU1413620A1 - Device for comparing numbers with tolerances - Google Patents

Description

(21) 4139919 / 24-24

(22) 10/21/86

(46) 07/30/88. Bul Number 28 (72) E, I. Wavruk

(53) 681.325.5 (088.8)

(56) USSR Copyright Certificate No. 783790, cl. G 06 F 7/04, 1979.

USSR Author's Certificate No. 1119005, cl. C 06 F 7/04, 1983.

(54) DEVICE FOR COMPARING NUMBERS WITH ADMISSIONS

(57) The invention relates to automation and computing and can be used in control and regulation systems for comparing the difference of two numbers with a third number. The purpose of the invention is to increase speed. The device contains elements AND 1-8, comparison schemes 9

and 10, counters 11-13, triggers 14-19, element OR 20, adder 21 modulo two, element AND-NOT 22, element ISH1-HE 23, decoder 24, bus 25, 26, respectively, the first and second numbers being compared, inputs 27 set tolerance values, 28 clock pulses input, 29 and 30 number inequality outputs, outputs 31-33 of the comparison result, respectively, within the tolerance, exceeding the tolerance value and equality to the tolerance value. The essence of the invention lies in the organization of summation and subtraction in the first and second counters, which speeds up the process of approximating numbers, and in the operational formation of the sign of exceeding the tolerance value. The invention allows to increase the speed of the device. 1 il. 1 tab.

"

sg zh az t t f

11413620

This invention relates to automation.

lakh tolerance 1. ab V a-b C d, equality of numbers to the tolerance value 1, a-b C numbers exceed the tolerance value i 1 a-bv abcd, where 1 g is correspondingly. These outputs, a, b, c, d - signals, respectively, on the first, second, third, fourth inputs of the decoder.

The dependences confirm the numerical values of D tolerance values (see table).

The device works as follows.

According to the initial setup signal (not shown), the triggers 14,15,17,18 are set to the zero state, the trigger 16 is set to the single state. The first and second numbers are written to counters 11 and 12 at inputs 25 and 26, the highest n-1 bits of the tolerance number are written to counter 13, the trigger 19 is the lowest bit of the tolerance number (the recording signals are not shown). The circuit 9 of the comparison, the inputs of which are connected to you - On the adder 21 modulo two for-25 with the strokes of the counters 11 and 12, produces

Ke and computer technology and can be used in control and regulation systems for comparing the difference of two numbers with the third number.

The purpose of the invention is to increase the speed.

The drawing shows a functional diagram of the proposed device. Yu

The device contains elements AND 1-8, circuits 9 and 10 of comparison, counters 11-13, triggers 14-19, element OR 20, adder 21 modulo two, element AND-NOT 22, element OR-NOT 23, decoder 5 24, inputs 25.26, respectively, of the first and second compared numbers, inputs 27 for setting the tolerance value, input 28 clock pulses, outputs 29 and 30 number inequalities, outputs 31-33 for the comparison result, respectively, within the tolerance, exceeding the tolerance value and equality for the tolerance value,

20

The parity feature (logical O) and oddness (logical 1) of the difference of numbers is reconciled. If there is an odd sign, the contents of the smallest

comparing the first and second numbers and forms a signal at one of its three outputs. In case of equality of the number, the element IZ opens, connected

compared numbers (in the counter 11 or 30 with the output of Equal circuit 9 compared to 12) in the first clock cycle increases by + 1, while in the following cycles the smaller and larger numbers of the compared numbers increase simultaneously. In the presence of the parity attribute -jj, a smaller increase in the number and a decrease in a larger number occurs at once starting from the first work cycle (the arrival of the first pulse on the bus 28), for example:

40

45

A 1010 ,, ,,, g, +1 2x0011j + 0001.J

Work cycle, А В №

010100011

110100100

210010101

310000110

401110111

The higher n-1 bits of the tolerance are recorded in the counter 13, the low-order bit in the trigger 19. The counter 13 constantly operates in the subtraction mode, which occurs only at the moment of simultaneous operation of the counters 11 and 12 in different modes (subtraction and addition) . The decoder 24 operates according to the following dependencies: the numbers in the precomparison of the first and second numbers and forms a signal at one of its three outputs. When the numbers are equal, the element FROM opens.

j

0

neither If the number entered in counter 11 is greater than the number in counter 12, element I2 is opened, connected to the output of More comparison circuit 9, and if the number in counter 11 is smaller, then element I1, connected to output of Less comparison circuit 9, opens.

The fallen bits of counters 11 and 12 are fed to the inputs of adder 21 modulo two, and if the numbers in c ZB-bits are of the same parity (both h-tn or odd), on its BBIXJ; The level of logic r 0 -5 is formed, which forms the level of the logical unit at the output of the NAND element (at the time of the output of the trigger 16, this is the one level). With different parities of numbers in the counters 11 and 12 at the output of the adder 21 - 1, at the output of the element AND-NOT 22 - O.

The pulses from the input 28 of the clock pulses arrive at the first inputs of the AND 1-3 elements, and if, for example, the AND 1 element is open, the pulses go to the summing input of the counter 11 and the input of the I7 element, which can be closed or opened depending on element exit status

0

five

IS-22. In the closed position of the element I7, only an increase in the contents of the counter 11 occurs, with an open - and a decrease in the contents of the counter 12. The impulse, the passage through the element OR 20, enters the input of the element I8 and depending on the state of the output of the element NID 22 passes or does not pass the input of counter 13 to the input. At the same time, this first impulse arrives at the input of element AND 5, and at a single output state of the element IS-NOT 22 records a single level in trigger 17, on the trailing edge of the first pulse trigger 16 is reset to zero It is a state that holds the NAND element 22 in a single state and does not allow the contents of trigger 17 to change. After that, the counter 11 operates in the summation mode, and the counters 12 and 13 operate in the subtraction mode. The pulses at the inputs of the counters 11-13 are received until the comparison circuit 9 generates the signal Equals. If all the outputs of the counter 13 are set to zero information before generating the signal Rav35

but at the output of the SHSHE-23 element for the fourth element I, a single signal distinguishes, which sets trigger 18 into one state, identifying that the difference in numbers exceeds the limit. In the case of an odd difference of the numbers at the output of the adder 21 modulo two, the level of the logical unit, at the output of the NAND element 22, the level of the logical zero, and the first pulse from the output of the element OR 20 will not change the contents of trigger-d0 hera 17, and its back front sets trigger 16 to zero.

When receiving a signal at one of the outputs 31-33, the control unit j of the system (not shown) stops the formation of pulses at the input 28.

right so that, in order to improve speed, the third, fourth, fifth and sixth triggers, the seventh and eighth AND elements, the modulo two adder, the AND – NO element, the OR – NOT element, the decoder, are entered into it. the low-order outputs of the first and second counters are connected to the inputs of a modulo-two adder, the output of which is connected to the first input of the NAND element, the output of which is connected to the nepBi iM inputs of the fifth, sixth, seventh and eighth elements And, the output of the first element And connected with the second input of the nth element And, the output of which is connected to The second input of the second counter, the output of the second element I is connected to the second input of the sixth element I, the output of which is connected to the subtractive input of the first counter, the output of element 1Ш1 is connected to the second inputs of the seventh and eighth elements And synchronous. the house of the third trigger, the information input of which is connected to the input of the logical zero of the device, and the output is connected to the second input of the NAND element and the third input of the seventh AND element, the output of which is connected to

Similarly, the device operates in the More mode, except that the counter 12 operates in the summation mode, and the counter 11 - in the subtraction mode, and with different parity of numbers, the subtraction input of the counter 11 in the first clock does not receive a signal (O - at the output of the AND- NOT 22). The comparison circuit 10 is intended to compare the tolerance value with the characteristic formed on the trigger 17.

Claims (1)

Invention Formula A device for comparing numbers with tolerances contains three counters, two comparison circuits, six AND elements, two triggers and an OR element, the input of the device’s clock pulses connected to the first inputs of the first, second and third elements AND, the second inputs of which are connected respectively to the outputs of exceeding the second number, exceeding the first number and the equality of the first comparison circuit, the outputs of the first and second elements AND are connected to the inputs of the OR element, the installation inputs to the one state of the first and second tr, respectively the first and second counters, the outputs of the bits of which are connected to the inputs of the first and second groups of the first matching circuit, respectively, and the information inputs are connected to the inputs of the first and second compared numbers of the device, respectively, the outputs of the first and second triggers are outputs of the device number inequality, the output of the second comparison circuit is connected to the first input five about the fourth element And, I differ- 0 j 0 five right so that, in order to improve speed, the third, fourth, fifth and sixth triggers, the seventh and eighth AND elements, the modulo two adder, the AND – NO element, the OR – NOT element, the decoder, are entered into it. the low-order outputs of the first and second counters are connected to the inputs of a modulo-two adder, the output of which is connected to the first input of the NAND element, the output of which is connected to the nepBi iM inputs of the fifth, sixth, seventh and eighth elements And, the output of the first element And connected with the second input of the nth element And, the output of which is connected to The second input of the second counter, the output of the second element I is connected to the second input of the sixth element I, the output of which is connected to the subtractive input of the first counter, the output of element 1Ш1 is connected to the second inputs of the seventh and eighth elements And synchronous. the house of the third trigger, the information input of which is connected to the input of the logical zero of the device, and the output is connected to the second input of the NAND element and the third input of the seventh AND element, the output of which is connected to sync-input of the fourth trigger, the information input of which is combined with the information input of the fifth trigger, and the output is connected to the first input of the second comparison circuit, the second input of which is combined with the first input of the decoder and connected to the output of the sixth trigger, the installation input of which is the input the lower bit of the tolerance yjcfpoAcTsa, the output of the eighth element And is connected to the subtractive input of the third counter, informational inputs of which The entrances are the higher tolerances of the device, as well. the outputs of the bits are connected to the inputs of the element i BL-NOT, the output of which is connected to the synchronous input of the fifth trigger, the output of which is connected to the second inputs of the fourth And element and the decoder, the outputs of the third, fourth And elements are connected respectively to the third and fourth inputs of the decoder, the outputs which are outputs of the result of the comparison with the tolerance of the device.