RU2052893C1 - Device for discrimination of first and last pulses in burst - Google Patents

Abstract

FIELD: pulse equipment. SUBSTANCE: device for discrimination of first and least pulses with time interval equal to time speel between these two pulses provides for formation by third AND gate 9 of pulse burst with duration determined by coincidence time of controlling pulses of burst with pulses of synchronization, for delay of these pulses by gate 10 for time τ exceeding period T of repetition of these pulses and for selection by univibrator 6, differentiator 3, first delay element 1, binary counter 2, NOR gate 4, first AND gate 5, NOT gate 7 and AND gate 8 of first and last pulses of delayed burst correspondingly. EFFECT: expanded application field, enhanced functional reliability. 2 dwg

Description

 The invention relates to a pulse technique and can be used in automation devices and computer technology.

 A device for isolating the first and last pulses in a packet, containing the first and second triggers, the first and second NAND elements, the output of the first of which is connected to the first output bus and to the synchronization input of the first trigger, the inverse output of which is connected to the first input of the first element AND-NOT, the second input of which is connected to the first input bus and the synchronization input of the second trigger, the information input of which is connected to the second input bus, an OR-NOT element, the first input of which is connected to the third input of the first AND-NOT element, with the direct output of the second trigger and the information input of the first trigger, the reset input of which is connected to the output of the OR-NOT element, the second input of which is connected to the synchronization input of the second trigger, the inverse output of which is connected to the first input of the second AND-NOT element, whose second input is connected to the direct output of the first trigger, and the output to the second output bus.

 The disadvantage of this device is its low noise immunity, due to the possibility of spurious impulses associated with the presence of impulse noise on the input bus clock pulses.

 The closest in technical essence and the achieved effect is a device for separating the first and last pulses in a packet, containing the first and second D-flip-flops, the inverse output of the first of which is connected to the first input of the first AND-NOT, the output of which is connected to the first output bus and With the input of the first D-flip-flop, the direct output of which is connected to the first input of the second AND-NOT element, the output of which is connected to the second output bus, the second input with the inverse output of the second D-flip-flop, the D-input of which is connected to the control bus, direct output with the D-input of the first D-trigger, with the second input of the first AND-NOT element and with the first input of the OR-NOT element, the output of which is connected to the R-input of the first D-trigger, the second input with the C-input of the second D-trigger and with the third input of the first AND-NOT element, a clock bus, a single vibrator, an OR element, the first and second AND elements, the first input of the first of which is connected to the clock pulses, the second input with a control bus, with the first input of the second AND element, the second the input of which is connected through a one-shot to the output of the first element And and the first input of the OR element, the second input of which is connected to the output of the second AND element, the output with the D-input of the second D-trigger.

 However, this device also has the disadvantage associated with the mismatch between the duration of the packet and the time of allocation of the first and last pulses in the packet and the formation of pulses of different durations due to the delay in the allocation of the last pulse in the packet.

 To eliminate this drawback, a device is proposed for separating the first and last pulses in a packet, containing a series-connected element OR-NOT and a first element AND, the output of which is connected to the first output bus of the device, a second element And, the output of which is connected to the second output bus of the device, and one-shot, introduced in series connected the third element And, the first and second inputs of which are connected to the clock bus and to the control bus, respectively, and the output is also connected to the input of the one-shot, and a binary counter, the first output of which is connected to the second output of the first AND element, and the other outputs are connected to the corresponding inputs of the OR element, NOT connected in series to the differentiation unit, the input of which is connected to the input of the one-shot device, and the first delay element, the output of which is connected to the installation input binary counter, the element is NOT, the input and output of which are connected to the output of the single-shot and the first input of the second element And, respectively, and the second delay element, the input and output of which is connected to the output of the rd AND gate and to the third and second inputs of first and second AND gates, respectively.

 Figure 1 presents the structural diagram of the device; figure 2 diagrams of stresses explaining his work.

 A device for extracting the first and last pulses in a packet contains the first 1 and second 10 delay elements, made, for example, in the form of delay lines, a binary counter 2, made, for example, on a chip type K155IE5, with a memory capacity selected based on the number of pulses in a pack, a differentiation unit 3, made, for example, in the form of a differentiating circuit, an OR-NOT 4 element, made, for example, on a chip type K155LE1, the first 5, second 8 and third 9 elements And made, for example, on chips type K155LI, single vibrator 6 execution enny, for example, on a chip type K155AG1, NOT element 7, made for example on a chip type K155LN1, first 11 and second 12 output device bus, bus 13 and clock bus 14 control.

 In this case, the third element And 9 is connected in series, the first and second inputs of which are connected to the bus 13 of the clock pulses and to the bus 14 of the control, and the output is also connected to the inputs of the second delay element 10 and one-shot, and a binary counter 2, the first output of which is connected to the second the input of the first element And 5, and the other outputs are connected to the corresponding inputs of the element OR NOT 4, the output of which is connected to the first input of the first element And 5, the third input of which is connected to the combined second input of the second element And 8 and the output of the second delay element 10, and the output is connected to the first output bus 11 of the device, a differentiation unit 3 is connected in series, the input of which is connected to the output of the one-shot 6, and the first delay element 1, the output of which is connected to the installation input of the binary counter 2, the input and output of the element is NOT 7 connected to the output of the one-shot 6 and the first input of the second element And 8, respectively.

 The device operates as follows.

At the initial moment of time, from the bus 13 clock pulses, only the first input of the third element And 9 receives a sequence of U ₁ (see Fig. 2, a) synchronization pulses with a repetition period T, so the voltage U _{2 is} generated at the output (see Fig. 2 , b) logical "0". In the case of the input from the input bus 14 to the second input of the third element And 9 of the first pulse of the packet U ₃ (see Fig. 2, c), for example, ahead of the corresponding synchronization pulse U ₁ , the first positive pulse U _{2 is} generated at the output of the third element And 9 (see Fig. 2, b) of duration τ _u , determined by the coincidence time of the first pulse of the burst U ₃ (see Fig. 2, c) with the corresponding pulse U ₁ (see Fig. 2, a) of the synchronization that goes to the inputs the second delay element 10, a single vibrator 6 and a counting input of a binary counter 2. At the output of a single vibrator 6 with a time constant τ _o , which is selected from the condition T + τ _{u >>} τ _o ,> T, a voltage U ₄ (see Fig. 2, d) of logical "1" is formed, which is supplied to the inputs of the element HE 7 and differentiating element 3. At the output of element NOT 7, a voltage U _{5 is} generated (see Fig. 2, e) of a logical "0", which, entering the first input of the second element And 8, closes it, and at the output of the differentiating element 3 in the form of a pulse U ₆ (see FIG. 2, f), the result of differentiation of the pulse front U ₄ (see FIG. 2, d) is generated, which is fed to the input of the first delay element 1. At the output of the first delay element 1, a positive pulse U ₇ delayed for a time τ ₃₁ is generated (see FIG. 2, g), which is supplied to the installation input of the binary counter 2 and transfers it to its initial state. The value of τ ₃₁ is selected based on the response time of the binary counter 2.

In case of coincidence at the first and second inputs of the third element And 9 of the second pulse U ₃ (see Fig. 2, c) of the packet with the corresponding pulse U ₁ (see Fig. 2, a) synchronization, a second positive pulse U ₂ is formed at its output (see Fig. 2, b), which enters the inputs of a single-shot 6, the second delay element 10 and the counting input of the binary counter 2, realizing by its front an increase in the amount of information of the latter by one and forming a positive voltage U ₈ at its first output ( see figure 2, h) logical "1" if there is left on it GOVERNMENTAL outputs logical voltage "0" is input at the respective inputs of OR-NO element 4. The output of OR-NO element 4 is formed voltage U ₉ (see FIG. 2, i) the logical "1" is supplied to the first input of the first element And 5, the second input of which from the first output of the binary counter 2 also receives the voltage U ₈ (see figure 2, h) logical "1".

At the same time, at the output of the second delay element 10, a pulse train U ₁₀ delayed by τ ₃₂ is formed (see FIG. 2, k), the delay value of which is selected from the condition T + τ _u > τ ₃₂ > τ _o In the case of the formation of the second element 10 at the output delays of the first positive pulse U ₁₀ (see Fig. 2, k), which enters the third input of the first element And 5, the first pulse of the packet U ₂ delayed by τ _{32 is} generated at its output (see Fig. 2, b) and the form of the pulse U ₁₁ (see figure 2, l) is supplied to the first output bus 11 of the device.

In case of coincidence at the first and second inputs of the third element And 9 of the third pulse U ₃ (see Fig. 2, c) of the packet with the corresponding pulse U ₁ (see Fig. 2, a) synchronization, a third positive pulse U ₂ is formed at its output (see Fig. 2, b), which is fed to the inputs of the second delay element 10, one-shot 6 and the counting input of the binary counter 2. In this case, the state of the one-shot 6 is maintained in the logical position "1", and the volume of the binary counter 2 is increased by one, resulting in the formation at a first output voltage U ₆ (see FIG. 2, s) ogicheskogo "0" and at its second output a logic "1" voltages, which are applied to the second input of the first AND gate 5 and to one input of OR-NO element, respectively. At the output of the OR-NOT 4 element, the voltage U ₉ (see FIG. 2, and) becomes equal to a logical “0” and the second pulse U ₁₀ (see FIG. 2, k) does not receive a delayed burst to the first output bus 11.

When the first pulse and the second inputs of the third element And 9 coincide with the fourth pulse U ₃ (see Fig. 2, c) of the packet with the corresponding synchronization pulse, a fourth positive pulse U _{2 is} generated at its output (see Fig. 2, b), which is supplied to the inputs of the second delay element 10, one-shot 6 and the counting input of the binary counter 2. The state of the one-shot 6 is again maintained in the logical "1" position, and the amount of information of the binary counter 2 is again increased by one, which causes the formation of voltage on its first and second outputs ogichesky "1" is input to the second input of the first AND gate 5 and the OR-NO element corresponding input 4. The output of the NOR 4 voltage logic "0" does not change the element, the first AND gate 5 remains locked and third delayed pulse ₁₀ U ( see figure 2, c) to the first output bus 11 does not arrive.

In case of coincidence at the first and second inputs of the third element And 9 subsequent pulses U ₃ (see, Fig.2, c) of the packet with the corresponding synchronization pulses, the first element And 5 remains locked and the delayed pulses U ₁₀ do not arrive at the first output bus.

At the end of the burst of pulses on the input bus 14 at the output of the third element And 9, the formation of pulses U ₂ (see figure 2, b) stops and after a period of time τ _{o the one-} shot 6 returns to the logical "0" position. From the output of the one-shot 6 voltage U _{4 is} supplied to the input of the element NOT 7 and translates it into the logical position "1". At the output of element 7, a positive voltage U _{5 is formed} (see Fig. 2, e), which, passing to the first input of the second element And 8, passes the last delayed pulse U ₁₀ (see Fig. 2, k), which in the form of a pulse U ₁₂ (see figure 2, m) enters the second output bus 12 of the device.

In the case of the presence on the bus 13 clock pulses of impulse noise U ₁ (see Fig. 2, a) at the output of the third element And 9 the formation of a false pulse U ₂ (see Fig. 2, b) will not occur and the allocation of the first and last pulses in the pack will not be broken.

 Thus, the proposed device allows the selection of equal in duration of the first and last pulses in the packet with a time interval equal to the time interval between these pulses in the packet.

Claims (1)

 DEVICE FOR ISSUING THE FIRST AND LAST PULSE IN A PACK, containing the first element And whose output is connected to the first output bus, the second element And, the output of which is connected to the second output bus, the third element And, the first input of which is connected to the clock bus, the second input - with an input bus, a one-shot, and an OR element - NOT, characterized in that an inverter, two delay elements, a pulse counter, the counting input of which is connected to the input of a one-shot, with the output of the third AND element and with the input of the first element nta delay, the output of which is connected to the first inputs of the first and second AND elements, the second inputs of which are connected respectively to the output of the OR element - NOT and to the inverter input, and the third input of the first AND element is connected to the first output of the pulse counter, the other outputs of which are connected to the corresponding the inputs of the OR element are NOT, the reset input through the second delay element is connected to the output of the differentiating element, the input of which is connected to the output of the one-shot and to the inverter input.

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