SU1403062A1 - Device for transforming vector coordinates in three-dimensional space - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the construction of specialized processors for solving stabilization problems. The aim of the invention is the expansion of the class of tasks due to the possibility of rotation of the vector in three-dimensional space. The device contains a vector 1 rotation block, registers 2-4, adders-subtractors 5-10, counters 11-13, decoders 14-16, control block 17. Three counters and three decoders are introduced into the device, which provide tracking of corners. In the vector rotation block, all three coordinates are processed simultaneously with step 2 (K is an iteration constant). The condition under which (l is the size of the mantissas of the coordinates) eliminates the influence of the noncommutativity of the rotation matrices on the order of the reference angles. As a result, it is possible to set all angles of rotation from the axes of the original coordinate system, for example, from a gyro-stabilized platform, which is very important when solving problems of stabilizing various ship systems in rolling. 1 h. item f-ly, 2 ill. (О (Л с 4: о со о 05 ГС F

Description

g

FIG. f

The invention relates to computing and can be used in specialized vector coordinate converters in three-dimensional space.

The purpose of the invention is to expand the class of real-time tasks by allowing the vector to rotate in three-dimensional space.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a control block diagram.

The device contains a block of 1 vector rotation, the first 2, the second 3 and the third 4 registers from the first to the sixth sum. Matrices -readers 5--10, the first AND, the second 12 and the third 13 counters, the first 14, the second 15 and the third 16 decoders, control block 17, inputs 18-20 of the first, second and third arguments, respectively, inputs 21-23 of the first iBoro, second and third corners, a group of clock inputs 24, outputs 25-27 of the first, second and third transforms - Mept, output 28 prizpaka end of the return), the second and third outputs 29 of the control unit, the first group of outputs 30 of the control unit alenie.

The control unit forms the first 31, second 32 and third 33 elements AND, first 34, second 35 and third 36 triggers, fourth to thirteenth elements AND 37-46, distributor 47 pulses, element OR 48, quadruple element AND 49 and element NOT 50 .

The device works as follows.

The coordinate transformation algorithm is

X, +,; (, + LeU ,, 2-У, - +, У, -. ЕХ, 2- + Ау -2Z, +, + AeX,., 21 |;. + 1 Н - 2;

e.

  1 L ta.1 - {- f, v, 8} -L:

(-), + 1 (-),

, 1, 2, ..., L / 2 / g / 2

 , 0 Ks

I sign) with ACh -

(one)

|)., e () e;

 -H -1

O for x | s, 0

L f signB with 10 when e, 0; a –hh at e,

10 when e, 0 where X, CC, Z

the vector on the axis of the coordinate system of the original nat;

n is the size of the mantissa of the coordinates X, Y, Z.

Before the patchom of calculations, the registers 2-4 of the projection of the vector Xf, Y, Z- on the axis of the original coordinate system, and counters 11-13, the angles φ, е, в, on which the initial coordinate system is deployed, are entered. The signal "Work received on one of the inputs of the group of clock inputs 24, in b; 1 17 control produces control signals from subtractors 5-10 and sync series shift

five

five

information in registers 2–4 and in block 1 of vector rotation at each iteration, coordinates Xi +, Y, + |, Z, i are obtained as a result of simultaneous rotation of the coordinate system by angles, and in accordance with algorithm (1). On subtractors x 5-7, the values of XeZ, 2 are calculated respectively; 02 U / - f Xi-2; LZ, and on adders-vychitate0 l x 8-10 respectively receive coordinates

, + h + H Y 52 + LH.X X2, Z, + i S; i-lh Y ,, rewritable in registers 2-4, respectively. The shifted coordinate values,, Z, 2 are obtained directly from the second outputs of registers 2-4. At the end of each iteration, the angle quantum is subtracted from the counters 11-13 by the counting inputs, and the calculation process is repeated at the new SRI value (.

When a corner is fully processed, the corresponding decoder triggers, by a signal of which the control unit 17 turns off the control signals of the corresponding totalizer subtractors, and the counter input of the corresponding counter is turned off. Thereafter, rotation is performed only at non-zero angles. When all angles are completely worked out, all the operators of the direction of rotation become zero and the calculations in accordance with algorithm (1) are reduced. At the output 28 of the control unit 17, a turn end signal is set and output 29 of the series of information shift in registers 2-4 is stopped. The projections of the vector in the unfolded coordinate system are removed from the outputs 25-27 of the device.

The control unit operates as follows. At input 24, the control unit receives a continuous synchronization 24.2, according to which pulses with periods equal to the duration of the iteration are generated in the pulse distributor 47, as well as the signal "Operation 24.1", which in the first iteration cycle on the And 46 element generates a device start pulse. At this pulse, at the zero output signals of the decoders, the And 31-33 elements set the triggers 34-36 to one state. The elements And 37-42 generate control signals for the adders 0 and the subtractors 5-10. The characters “- | - and“ - designate the operation modes of the totalizer-subtractor, and the number corresponds to its position in FIG. 1. On elements I 43-45, in the last cycle of each iteration, pulses 2 are produced, which are applied to

5 counting inputs counters 11 -13. After working off any angle B by a signal from the corresponding decoder at the input “Ex. LH corresponding trigger (34-36)

0

five

0

five

ycTaHaBvinBaercH to the zero state, on the elements AND 37-42, the control signal generation stops, and on the And 43-45 elements the generation of the corresponding counting pulses stops. The element OR 48 opens with single outputs of the triggers 34-36 and allows the output through the element AND 49 at the input 24.2 of the shift series to the registers 2-4. At the output 29 of the distributor 47, the pulses necessary for synchronizing its operation are output to the vector turning unit 1. After all the corners have been worked out, the triggers 34-36 are set to the B zero state, the elements OR 48 and I 49 close and turn off the information shift in the turn unit registers. The output of the element OR 48 inverted on the element NOT 50 is a signal of the sign of the end of the vector rotation.

Claims (2)

1. A device for converting vector coordinates in three-dimensional space, containing the idea of a vector rotation block, first counter, first decoder and control block, the vector rotating block contains three registers and six detractors, and the inputs of the first, second and third arguments of the device connected to the first information inputs of the first, second and third registers, respectively; the outputs of the first, second and third registers are connected to the inputs of the first operands of the first, second and third, respectively totalizers-subtractors, the outputs of which are connected to the inputs of the first operands, respectively, of the fourth, fifth, sixth adders-subtractors, whose outputs are connected to the second information inputs of the first, second and third registers, respectively, of the first output of the first group of outputs of the control unit the fifth and sixth adders-subtractors, the second output of the first group of outputs of the control unit is connected to the input of the choice of the operation code of the first and third adders-subtractors, the third output The first group of outputs of the control unit is connected to the input of the selection of the operation code of the second and fourth totalizer-subtractors, the first output of the control unit is the output of the sign of the end of the device rotation, the second and third outputs of the control unit are connected respectively to the clock inputs and shift inputs of the first, second and second of the third register, the group-clock inputs of the device are connected to the same group of inputs of the control unit; the outputs of the fourth, fifth, and sixth summers-subtractors are the outputs of razovannyh first, second and third arguments apparatus respectively The relative lichayuschees in that, with a view to spreading class of rendered tasks due to the possibility of vector rotation in three-dimensional space, two, counters and two decoders are additionally introduced, the output of the first register being connected with a shift by D bits towards the lower bits (L is an iteration constant) with the inputs of the second operands of the second and third summers of the subtractors, the output of the second register is connected with a shift by K. bits towards the lower bits with the inputs of the second operands of the fourth and sixth summators of the subtractors, the output of the third register is connected with the shift on the K bits in the direction of the lower bits with the inputs of the second operands of the first and fifth adders-calculators, the inputs of the first, second and third corners of the device are connected to the recording inputs of the first, second and third counters, respectively, whose outputs are connected to the inputs the first, second and third decoders, respectively, the outputs of which are connected to the group of inputs of the signs of the zero angle of the control unit; the outputs of the old bits of the first, second and third counters are connected to the group of inputs of analyzing the characters of the unit pack The first, second, and third outputs of the second group of outputs of the control unit are connected to the counting inputs of the first, second, and third counters, respectively. 2. The device according to claim 1, characterized in 0 that the control unit contains a pulse distributor, three flip-flops, fourteen AND elements, an OR element and a NOT element, the first, second and third inputs of the group of inputs of the zero signs of the control unit are connected to the first inverse 5 inputs of the first, second and third elements, respectively with the reset inputs of the first, second and third triggers, respectively, the first input of the group of inputs for character analysis is connected to the first direct input of the fourth and the first inverse input of the fifth And elements, the second input of the input group of the character analysis is connected to the first input of the sixth and first inverse input of the seventh And elements, the third input of the group of character analysis inputs is connected 5 with the first direct input of the eighth and the first inverse. The input of the ninth elements And, the second inputs of the fourth and fifth elements And connected to the output of the first trigger, the second inputs of the sixth and seventh elements And connected to the output of the second trigger, 0 second inputs of the eighth and ninth elements And connected to the output of the third trigger, the installation inputs of the first, second and third triggers connected to the outputs of the first, second and third elements And the outputs The first, second, and third flip-flops are respectively connected to the first, second, and third inputs of the OR element, the output of which is NOT connected to the first output of the control unit through the element, the first. the second and third outputs of the second group of outputs of which are connected to the outputs of the tenth, eleventh and twelfth elements I, respectively, the first inputs of which are connected to the outputs of the first, second and third triggers, respectively, the second inputs of the tenth, eleventh and twelfth elements And the output of the pulse distributor, the second output of which is connected to the second output of the control unit, the third output of the pulse distributor is connected to the first input the thirteenth element And, the second input of which and the start input of the pulse distributor are connected to the first and second inputs of the group of clock inputs of the control unit, the third input of the group of clock inputs of the control unit is connected to the first input of the fourteenth element And, the second input of which is connected to the output of the OR element, and the output connected to the third output of the control unit; the output of the thirteenth element I is connected to the second inputs of the first, second and third elements I. FIG. 2