RU2050021C1 - Device for displaying lines and arcs of screen of cathode-ray tube - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has control unit 1, clock 2, four reverse counters 3, 4, 5, 6, three multiplexers 7, 8, 10, constant generation unit 9, pulse counter 11, adder 12, decoder 13, read-only memory unit 15, two registers 14, 16, two digital-to-analog converters 17, 18, cathode-ray tube 19, processor 20. EFFECT: increased functional capabilities. 3 dwg

Description

 The invention relates to computer technology and can be used in the design of devices for displaying information on a CRT screen.

 The purpose of the invention is to improve the accuracy of the device.

 In FIG. 1 shows a block diagram of a device; figure 2 block decryption sectors; figure 3 octants and values of the logical function B for an arc with a direction of movement counterclockwise and clockwise.

 The device implements a method of forming vectors and arcs, which consists in the fact that at each step, the sign of the previously calculated evaluation function determines and transitions to the next point of the vector or arc, and also forms a formula by which the evaluation function is calculated for the next step.

 The formulas for moving to the next point and calculating the evaluation function are uniquely determined by the fact that in which octant of the coordinate plane is the current point of the vector or arc, and for an arc, an additional condition is the direction of movement along the arc.

 In the case of a vector, for all current points, the octant is determined by the components of the increments of the vector DX and DУ, for an arc, the octant of the current point is determined by the components of the current radius vector DX (i) and DY (i), where i 1 N, and N is the number of points of the vector or arc.

The calculation formulas for the vector are as follows:
D (o) SY˙DY2˙DY + SX˙DX2˙DX (1)
If D (i-1) <0, then D (i)
D (i-1) + SDY˙SX˙DX + SDX˙SY˙DY
X (i) X (i-1) + SDX˙SX
Y (i) Y (i 1) + SDY˙SY (2)
If D (i-1) ≥ 0, then D (i)
D (i-1) + (SDY SDA) ˙SX˙DX +
+ (SDX SDY) ˙SY˙DY
X (i) X (i-1) + SX
Y (i) Y (i-1) + SY (3) where D (i-1) and D (i) are estimated function at the (i-1) and i-th steps, respectively,
D (0) preliminary estimation function for the first step,
X (i), Y (i) coordinates of the point to which the transition is made at the i-th step,
X (i-1), Y (i-1) coordinates of the point of the previous step
SX, SY, DX2, DY2, SDX, SDY functional coefficients determined from the conditions:
SX sign (DX 1 if DX ≥ 0.

-1 if DC <0 (4)
SY sign (DY 1 if DY ≥ 0
1- if DY <0
DX2 1 if DX <DY |
-1/2 if DX | ≥DY |
DY2 -1/2 if DX | <DY |
1 if DX | ≥DY |
SDX 0 if DX | <DY | (5)
1 if DX | ≥DY |
SDY 1 if, DX | <DY |
0 if DX | ≥DY |
The calculation formulas for the arc are of the form
D (O) 3/4 + SDY˙DY2˙DY +
+ SDX˙DX2˙DX (6)
If D (i-1) ≥ 0 V, then D (i)
D (i-1) + SDY˙DY (i-1) +
+ SDX˙DX (i-1) + 5/2
X (i) X (i-1) + SDX
Y (i) Y (i-1) + SDY (7)
If D (i-1) <0 V, then D (i) D (i-1) +
+ ADX˙DX (i-1) + ADY˙DY (i-1) + 3/2
X (i) X (i-1) + ADX
Y (i) Y (i-1) + ADY (8)
If D (i-1) ≥ 0 V, then D (i)
D (i-1) + ADY ˙DY (i-1) +
+ ADX˙ DX (i-1) + 3/2
X (i) X (i-1) + ADX
Y (i) Y (i-1) + ADX (9)
If D (i-1) <0 V, then D (i)
D (i-1) + SDX ˙ DX (i-1) +
+ SDY ˙DY (i-1) + 5/2
X (i) X (i-1) + SDX
Y (i) Y (i-1) + SDY (10) where SX sign (DX) 1 if DX ≥ 0
-1 if DX <0 (11)
1 if DY ≥ 0
SY sign (DY) -1 if DY <0 (12)
Additional logical functions A, B and functional coefficients ADX and ADY are introduced into the formulas. The values of these coefficients, functions A and B, as well as the coefficients SDX, SDY, DX2, DY2 depend on the direction of movement along the arc.

Logical function B takes the value 0 or 1 depending on the octant at which the current point of the arc is located. Figure 3 shows the octants and values of function B for an arc with a direction of movement counterclockwise and clockwise
When the current point passes from one octant to another (which corresponds to a change in the value of function B), it is necessary to recalculate the value of the evaluation function using the following formulas:
B _ → B: D (i-1) D (i-1)
SX ˙DX (i-1) / 2 SY˙DY (i-1) / 2
B _ → B: D (i-1) D (i-1)
SX˙DX (i-1) SY˙DY (i-1) (13) and only then continue the iterative process.

 The device contains a control unit 1, a clock generator 2, reversible counters 3 and 4 coordinates, reversible counters 5 and 6 increments of vectors, multiplexers 7, 8, a contact forming unit 9, multiplexer 10, pulse counter 11, adder 12, decoder 13 (sectors ), register (of flags of conditions) 14, block 15 of read-only memory, register 16 (addresses), digital-to-analog converters 17 and 18, cathode ray tube 19 (CRT).

 The device is running processor 20.

 The decoder 13 sectors contains blocks 21 and 22 of the X axis and the Y axis, the arithmetic logical unit 23, the operation sign unit 24, the read-only memory unit 25.

 The device operates as follows.

 The operation of the blocks is synchronized by the generation of 2 clock pulses by the generator, which make it possible to distinguish the beginning, middle, and end of a cycle.

 Upon receipt of the command from the processor 20, the control unit 1 stores the command code and generates the following sequence of control signals synchronized by clock pulses.

 At the first clock cycle of the vector or arc command, at the outputs of block 1, a pulse reception signal is generated, which is transmitted via the data bus to the input of incremental counters 5 and potential signals V / D and direction of movement along the arc clockwise / counterclockwise are set for the duration of the command coming to two of the address inputs of block 15, as well as to the input of the decoder 13 sectors.

 In the second cycle, the input of the reverse counter 6 of the increment DY receives from the output of unit 1 a pulse signal of reception DY.

The adopted values of DX and DY are fed to the input of the decoder 13 sectors, one of the outputs of which controls the multiplexer 10 to select the larger of DX | and DY |
In the third cycle, unit 1 generates a reception signal N to the pulse counter 11 either from the data bus in the case of an arc, or from the output of multiplexer 10.

 At the beginning of each clock, information is received from address decoder 13 of the sectors, register 14 and from the sign digit of the result of adder 12 to the address register 16. The decoder 13 generates a four-digit code, according to which 16 sectors are distinguished (see Fig. 3). Depending on the operation being performed, a vector or arc, in the latter case and on the direction of movement, every two sectors form one octant.

 The register (of flags of conditions) 14 generates two flag signals arriving at the address input of block 15 through the register 16, and fixing the clock cycle of calculating the initial value of the evaluation function and the clock cycle of its conversion when changing octants during the arc operation.

 The flag of the initial condition is set in the second measure, is reset after calculating the initial value of the evaluation function in the third measure.

 In the first half of each clock cycle, the block 15 at the input address generates, in accordance with the above formulas, the control signals supplied to the adder 12, multiplexers 7 and 8, the constant generation unit 9, reversible increment counters 5 and 6, and coordinate counters 3 and 4.

These signals determine:
on the adder 12, the number and signs of the operands involved in the calculation of the evaluation function D (i);
on multiplexers 7 determine the choice of the value of 1 or 1/2 of the functional coefficients SX and SY;
on block 9, the choice of one of the four constants 0.3 (4.5) 2, 3/2, formed by the corresponding potentials at the information inputs of the multiplexer, which actually makes up block 9;
on counters of 5 and 6 increments and counters of 3 and 4 coordinates, the presence and sign of the corresponding increments.

 Thus, the inputs of the adder 12 received SDX | ˙ | DX | SDY | ˙ | DY | constant from the output of the same adder D (i-1).

 In the middle of each clock cycle, the adder 12 starts to calculate according to the formula (D, i) required from (2, 3, 7-10). At the same time, there is a change in the values on the reversible counters 3, 4, 5, 6.

 In the third measure, as described above, when the flag of the initial condition is set, D (0) is calculated by formulas (1) or (6) without changing the values of DX, DY, X, U coordinates.

 From the fourth step, an iterative process of step-by-step implementation of a vector or arc is carried out. In each of these calculated clocks, the content of the counter of 11 pulses decreases by one unit. When the counter is reset, it gives block 1 a signal about the completion of the current operation.

 In the process of forming an arc when changing the octant, i.e. changing the value of function B, the recalculation flag is set, and in the next step, the value of the estimated function D (i-1) is recalculated by formulas (13) without changing the contents of counters 5, 6, 3 and 4 of increments and coordinates, or the counter of 11 pulses .

 The control signals allocated by the decoder unit 13 are generated at the output of the permanent memory unit 25.

 The input signals are the values of the increments DX and DY, as well as the control signals V / D and DIR from block 1.

 Along with the generation of a 4-digit sector code (one of the bits of this code has the value of function B) and, as mentioned above, the control signal of the multiplexer 10, the decoder 13, based on the sign of the number of value points received on the counter 11, generates a control signal of the count sign counter 11.

Block 13 generates signals of equality to zero, respectively, of the increments DX and DY, the equality signal DX | DY | and signal sign of the result of comparing the values of DX | and DY |
The proposed device provides a speed of formation of lines of both vectors and arcs of the order of 125 ns per point (the clock speed of the device is 8 MHz).

Claims (1)

 DEVICE FOR DISPLAYING VECTORS AND ARCS ON THE ELECTRON BEAM TUBE (CRT) SCREEN, containing a clock pulse generator, the first output of which is connected to the clock input of the control unit, the input-output of which is the input-output of the device, the first output of the control unit is connected to the first information inputs reversible vectors increment counters and reversible X and Y coordinate counters, the outputs of which are connected to the inputs of the digital-analog coordinate converters X and Y, respectively, whose outputs are connected to By using a CRT system, the first, second, and third multiplexers, the output of the third multiplexer is connected to the information input of the pulse counter, the output of which is connected to the control input of the control unit, the outputs of the reversible vector increment counters are connected to the information inputs of the first and second multiplexers, adder, first register, and a decoder, characterized in that, in order to increase the accuracy of the device, it contains a read-only memory block, a second register and a constant generation unit, the output of the first reg The device is connected to the control input of the second register and the address input of the read-only memory block, the control input of which is connected to the second output of the control unit connected to the reset input of the second register, the control input of the decoder and the second information inputs of the reversible counters of vector increments, the counting inputs of which are connected to the second output a clock generator connected to the clock input of the second register, the counting inputs of the reverse coordinate counters and the pulse counter and the clock input the adder, the output of which is connected to the first control input of the first register and the reset input of the adder, the information inputs of the adder are connected to the outputs of the first and second multiplexers and the constant forming unit, the control input of which is connected to the first output of the read-only memory unit, which is connected to the control inputs of the adder, the first and the second multiplexers and reversible counters of increments of vectors, the second and third outputs of the read-only memory block are connected to the control inputs of the reverse counters rdinat, information inputs of the decoder to the outputs of reversible counters of increments of vectors, control input to the second output of the control unit, the first output of the decoder to the first information input of the second register, the second output to the control input of the pulse counter, the reset input of which is connected to the first output of the second register, the second output which is connected to the second information input of the first register, the third output of the decoder is connected to the control input of the third multiplexer, the information inputs of which are connected to the outputs of reverse counters of increments of vectors.

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