SU1388952A1 - Static register - Google Patents

Abstract

The invention relates to computing and is intended for the implementation of units and devices of digital computers using the methods of integrated technology. The purpose of the invention is to expand the functionality of the register by performing bitwise logical inequality and equivalence operations. All functions in the static register are performed on the basis of nine micro-operations (A1-A9 operators). To perform logical operations of three variables, logical operations of two or one variable are preliminarily implemented, and in the next cycle one of the operators (A1-A9) is additionally implemented. Similarly, logical operations of four variables are implemented. The register contains elements NOT 13, 14, n-bits, each of which consists of RS-flip-flop 1, elements AND-NO 4, 5, 6, 7, element OR. 1 ill., 1 tab.

Description

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The invention relates to computing and is intended for the implementation of KNOTS and devices of digital computers using methods of integrated technology.

The aim of the invention is to expand the functionality of the register by performing bitwise logical operations.

The drawing shows a static trigger circuit.

The table shows the register micro-operations.

The register contains in each bit of 1 RS-trigger on the elements AND-NOT 2, 3 and the first, second, third elements AND-NOT 4, 5, 6, the element NOT 7, the element OR 8, the first and second information inputs 9 , 10 and outputs 11, 12. In addition, the register contains the first and second elements) NOT 13, 14, control Yush, inputs 15-19, zeroing input, first and second inputs of the logic functions, inputs for recording information mom and inverse codes.

The device works as follows.

All functions in the static register are performed on the basis of nine micro-operations (operators) AI-Ad.

Before the information is received by the AI operator, the register is reset, i.e., by applying a logical unit to input 15. Accordingly, a low voltage level is established at the output of the first element NOT 13. RS-triggers are set to the zero state. A high voltage potential appears at the outputs of the 12i - 12h register.

Information is received in the forward code by the operator Ar, i.e., a high voltage potential is fed to input 18, the AND-HE element 4 is opened, and the input information is fed to the first S input of RS flip-flop 2 (3). As a result, the function is performed:, where RG is the contents of the register. However, the RG Oh, therefore: X.

Information input in the inverse code is carried out by the operator AZ. After supplying the logical unit to input 19, an AND-HE element 5 is opened, to the first input of which the inverse information of the input code is supplied. As a result, an operation is performed. When we get.

Logical operations are mainly performed in RS-triggers 2, 3, the characteristic equation of which is SVRQ

Bitwise logical operations from two variables are performed as follows.

The first variable X is in the register, and the second Y is present at inputs 9i-9 ".

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If the operator A2 is implemented, the result is a disjunction, e. RG - i RG -Vy. However, therefore, RG: XVy- The result of the implementation of the disjunction operation is obtained at the outputs 11.1 - 11.P register. At the same time at the outputs of the 12. register we get the function.

In order to perform a bitwise conjunction operation, first of all, after setting the register to the initial state, the operator Az is realized, with which the inverse code of the first variable X is written. Next, the AZ operator is reimplemented, but the input

- 9-p gives the second operand Y. As a result, at the output of the 12p register, we get the conjunction function X & Y. The conjunction operation is also obtained when the AS operator is implemented, and the result of the operation also appears at the output of the 12.p register. For

0 implementations of the As operator should be given logical units to the inputs 17, 18, 19. At the same time, the AND-HE elements 4, 5, 6 are opened, the X-Y function is fed to the first 5-input RS-trigger, and the X function is fed to the second. As a result, we get the function at the forward output of the Pn, and at the output of the RS flip-flop — the function X-Y. With this implementation, the function of the conjunction must first have the register wrapped by the operator AI and the operands X and Y odQ should be fed to inputs 9 and 10 .

In the implementation of the operation of disjunction and conjunction, the operations of Pierce XVy and Scheffer X &

The modulo 2 operation of the two operands is implemented by the operator Hell. With this

5 aiming at inputs 19, 18, 16, 17 logical units are supplied. Operands X and Y are simultaneously fed to inputs 9 and 10, the AND-NE elements 4, 5, 6 are simultaneously opened, a high potential is removed from the second input of the element OR 8. As a result,

0 S-inputs of the RS-flip-flop a and the XY and XY functions appear respectively and at the output 11 of the register the result of the implementation of the function XY

g implementation of the function of equivalence. Note that before implementing the mod2 operation, the register should first be set to the initial state. With the help of AI-Ad operators, all logical operations of one and two are realized.

0 variables that can be easily obtained with a certain combination of functions listed in the table.

In order to perform logical operations with three variables, logical operations with two or one variable are preliminarily implemented, and in the next cycle one of the operators A | - Ad is additionally implemented. Similarly, logical operations of four variables are implemented.

Claims (1)

Invention Formula A static register containing the first element NOT and in each bit the first, second and third elements NAND and NOT the element and the RS flip-flop, whose outputs are the first and second information bits of the register, respectively, the first and second S-inputs RS - triggers in each bit OR element, outputs of the OR element and the NAND element of each bit are connected respectively to the first and second inputs of the second NAND element, the first input of the OR element is connected to the first input of the third NAND element and is the second information entry times and register element input of the AND-NO element of each bit is connected to the first input of the second AND-member each RA connected respectively to the outputs. . , the first and second elements AND-NOT, the first bit, the second inputs of the third elements the input of the first AND-NOT element is the IN-AND-NO of all bits combined and is the information input of the register bit, secondly with the first control input of the task Swarm input of the first element of the IS-NOT sub-logic functions, second inputs of the element to the output of the third element of the IS-NOT, com. OR all bits of the register connect the third inputs of the first elements of the IS-NOT of all 5 connected to the output of the second elerads unified, R-inputs RS -trigger NOT whose input is second all bits are combined and connected to the output of the NOT element, the input of which is a control zero-reset input, characterized in that, in order to enable the input of the logic functions, the third input of the first AND-NOT element of the last bit is a control input recording information directly Reni functionality 20 code, the second inputs of the second elements and NOT the execution count of the bit logical all bits is combined and is the inequality upfunctions and is equivalent to the input recording information in the second element of the non-inverse code is introduced into it. and each time the OR element, the outputs of the OR element and the NAND element of each bit are connected respectively to the first and second inputs of the second NAND element, the first input of the OR element is connected to the first input of the third NAND element and is the second information the register bit's input, the input of the NAND element of each bit is connected to the first input of the second NAND element of each . . , bit, second inputs of third elements the control input of the logic function assignment, the third input of the first NAND element of the last bit is the control input of the information recording in the forward Note, The symbol X denotes the resolution of the supply of both a logical unit and a logical zero.