JPH08227326A - Microcomputer - Google Patents

Abstract

PURPOSE: To increase the frequency of pulse to be counted and to speed up a microcomputer by inputting an output signal from one counting timer to a clock signal control means in the other counting timer. CONSTITUTION: A timer counter 8A including an AND gate 83A having three inputs is provided as a timer counter. A 3rd input terminal to which the AND gate 83A is added is connected to an output terminal T2 and an output signal O is supplied. A flip flop 78 in a timer counter 7 is turned to '1' at the time of writing '1' in an operation control circuit 70 as set data Da, and when a count pulse Pa is supplied during the output of a coincidence signal Ca to be an output from a comparator 77, the output O is inverted. The output O is supplied to the output terminal T2 and the AND gate 83A of the timer counter 8A. In response to the supply of the output O, an output clock X from an MPX 81 and output data Db from an operation control circuit 80, the AND gate 83A executes the AND operation of respective data and outputs a count pulse Pb to a counter 85.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a single chip microcomputer (hereinafter, single chip microcomputer) having a plurality of timer counters built therein.

[0002]

2. Description of the Related Art Generally, a timer counter incorporated in a single-chip microcomputer is used for measuring an arbitrary time and counting an input pulse from the outside, and each of these measurement / counting operations has one timer counter. It is executed as an independent timer counter. If the single-chip microcomputer incorporates two timer counters, one of them is used as a time measurement timer and the other is used as a count timer for counting external input pulses. There is also a method of counting external input pulses.

Here, an example of a single-chip microcomputer provided with the above-mentioned two built-in timer counters as a conventional microcomputer and used respectively for a time measuring timer and for counting an external input pulse will be described.

Referring to FIG. 4, which shows a block diagram of a conventional first general microcomputer of this type, this conventional microcomputer divides a clock X1 from an X1 terminal T1 by a predetermined dividing ratio. CPU2 and MPX7
Internal clocks XC and Xa to be supplied to 1 and 81, respectively
1, a frequency divider 1 for generating Xa2, Xb2, Xb2, a CPU 2 for performing processing in accordance with a program stored in a ROM 3 in synchronization with a clock XC, a ROM 3 storing a program for the CPU 2, and a data and address transmission The bus 4 has a bidirectional multi-bit length, signal lines 5 and 6 for transmitting a write signal W and a read signal R, and timer counters 7 and 8.

The timer counter 7 is composed of a 1-bit register and controls the operation of the counter 75.
0, MPX71, and 2-bit register MPX71
CLSEL 72 that selects the clock output by the
Input AND gate 73 and 2-input OR gate 74
, Counter 75, comparison value setting register 76, comparison circuit 77, flip-flop (F / F) 78, IN
And TT79.

Here, the write signal W is a signal which becomes "1" when data is written in these operation control circuits 70, 80, CLSELs 72, 82, comparison value setting registers 76, 86, and INTTs 79, 89. Yes, read signal R
Is a signal which becomes "1" when the data is read from the counters 75 and 85.

Next, the operation of the conventional microcomputer will be described with reference to FIG. 4 and FIG. 5 which shows an operation time chart. First, the CPU 2 instructs the timer counters 7 and 8 via the bus 4. Addresses and data are supplied, and in synchronization with the write signal W of the signal line 5, each register of the timer counters 7 and 8, that is, the operation control circuit 70,
Data is written to 80, CLSELs 72 and 82, comparison value setting registers 76 and 86, and INTTs 79 and 89, respectively. Further, in synchronization with the read signal R of the signal line 6, the address is output to the timer counters 7 and 8 via the bus 4 and the data is read from the counters 75 and 85. In addition, INTT79 or INTT
The interrupt processing is performed by the generation of the interrupt signal INT from 89. In this interrupt processing, the write signal W of the signal line 5 is set to "1" via the bus 4 and the interrupt flag corresponding to the generation of the interrupt signal INT, that is, INTT79 or INTT8.
After clearing the contents of 9, the interrupt processing routine corresponding to the interrupt signal INT stored in the ROM 3 is executed.

The writing of the data Da into the operation control circuit 70 is performed by the CPU 2 via the bus 4 in synchronization with the write signal W. Output data Da of the operation control circuit 70
Is "0", the output of the AND gate 73 is "0" and the counter 75 does not operate. When the data Da is set to "1", the counter 75 is initialized, the content of the F / F78 becomes "1", and the content of the INTT79 becomes "0".
At this time, the count pulse Pa output from the AND gate 73
Is the output of MPX71, and the counter 75 is MPX71
Counting is performed in synchronization with the rise of the output. MPX
Reference numeral 71 denotes clocks Xa1 and Xa supplied from the frequency divider 1.
2 as an input, and in response to the output signal of the CLSEL 72, one of the clocks Xa1 and Xa2 is A
Output to the ND gate 73. Writing to the CLSEL 72 is performed by the CPU 2 via the bus 4 in synchronization with the write signal W on the signal line 5.

The counter 75 has a comparison value setting register 76.
The count-up is performed in synchronization with the rising edge of the count pulse Pa until it matches the set value Ma of. The count value Na of the counter 75 is always supplied to the comparison circuit 77. Count value Na
When the rising edge of the count pulse Pa (hereinafter, the count pulse Pa) is input during the writing of the data Da′1 ′ into the operation control circuit 70 or the generation of the coincidence signal output from the comparison circuit 77, the OR gate 424 outputs Output reset pulse Ia
Is initialized by. The counter 75 can be read by the CPU
2 via the bus 4 in synchronization with the read signal R on the signal line 6.

The comparison value setting register 76 is a CLSEL7.
2 is a register for setting an arbitrary set value Ma corresponding to the measurement time calculated from the frequency of the selected clock. Writing to the comparison value setting register 76 is performed by the CPU 2 on the bus 4
Via the write signal W. Set value M
a is always supplied to the comparison circuit 77.

The comparison circuit 77 always compares the comparison set value Ma with the count value Na, outputs a match signal Ca'1 'when both values match, and outputs F / F with the next count pulse Pa.
Control signals are output to 78, INTT 79, and OR gate 74. The F / F 78 becomes "1" by writing "1" in the operation control circuit 70, and when the count pulse Pa is input from the comparison circuit 77 during the output of the coincidence signal Ca, its output Oa is inverted. This output Oa is output to the terminal T2.

The INTT 79 becomes "0" by writing "1" as the data Da of the operation control circuit 70, and when the count pulse Pa is inputted from the comparison circuit 77 during the output of the coincidence signal Ca, the output INTa becomes "1". 'Is the interrupt flag. Also, INTa is always CPU2
Is supplied to the CP, and when this INTa becomes '1', the CP
The contents are cleared by the interrupt processing performed by U2. The timer counter 8 has a configuration in which a pulse TIb input terminal T3 to be counted is added to the configuration of the timer counter 7, and the pulse TIb can be selected as the count pulse Pb corresponding to the set value of CLSEL84. Other than that, the description is omitted because it is the same as the timer counter 7.

Here, for convenience of explanation, the timer counter 7 is a time measuring timer for measuring an arbitrary time, and the timer counter 8 is a count timer for counting an external input pulse. Also, both the time measuring timer and the count timer are 8-bit timer counters.

Next, the counting operation of the external input pulse of the conventional microcomputer will be described with reference to FIG. 5 showing the operation time chart. First, the operation modes of the timer counters 7 and 8 are set. Timer counter 7
The operation setting of is the output program (command) from ROM3
The CPU 2 decodes the IP and CLSEL 7 via the bus 4.
This is done by setting data in each of the 2 and the comparison value setting register 76. The CLS is set in the comparison value setting register 76.
Data “n” (measurement time = clock frequency × (n + 1)) as an arbitrary set value Ma corresponding to the measurement time calculated from the clock frequency of the clock Xa selected by the EL 72.
Set. Further, the CLSEL 72 has a counter 75.
Uses the reference clock for counting up as clock Xa1,
Data for selecting either one of the two types of clocks Xa2 is set.

Similarly, the operation of the timer counter 8 is set by the CPU 2 decoding the program in the ROM 3 and the CLS.
This is performed by setting data in each of the EL 82 and the comparison value setting register 86. In the comparison value setting register 86,
The maximum value'FFH 'is set as the set value Mb. Also,
The CLSEL 82 outputs the clock Xb to the output of the MPX 81.
In addition to 1 and Xb2, data for selecting the pulse TIb is set.

Next, the operation of the timer counters 7 and 8 is started. First, the CPU 2 sets the output data Db of the operation control circuit 80 according to the decoding result of the program IP.
Set to 1 '. At this time, the counter 85 is initialized to '00H', the F / F 88 becomes '1', and the INTT 89
Will be '0'. The counter 85 counts up in synchronization with the pulse TIb until the count value Nb matches the set value Mb'FFH 'of the comparison value setting register 86.

Next, the CPU 2 similarly operates in the operation control circuit 7
The output data Da of 0 is set to '1'. At this time, the counter 75 is initialized to "00H" and the F / F78 is set to "00H".
It becomes 1'and INTT79 becomes '0'. Counter 7
5 counts up in synchronization with the count pulse Pa until it matches the set value Ma'n 'of the comparison value setting register 76. At the next count pulse when the count value Na of the counter 75 becomes n, the count value Na becomes the initial value '00H', and F
/ F78 is inverted to "0". At this time, INTT7
9 becomes '1' and an interrupt occurs. Occurrence of interrupt is CP
The message is sent to U2, and CPU2 performs an interrupt process and INT79.
Then, the CPU 2 executes the INTTa interrupt processing routine of the ROM 3. CP in ITTT interrupt processing routine
U2 obtains the count value = 0FH of the count pulse TIb from the outside by reading the count value Nb of the counter 85 in operation.

That is, the period from the start of the operation of the timer counter 7 which is a time measuring timer to the generation of the INTT 79 is the measuring time, and the timer counter 8 which is a count timer is externally operated until the interruption of the time measuring timer occurs. The counted pulse TIb is counted.

Next, referring to FIG. 6, which shows a block diagram of a conventional second microcomputer in which components common to those of FIG. 4 are designated by common reference characters / numerals, the second conventional microcomputer is referred to. The difference between the microcomputer and the first microcomputer described above is that a timer counter 8B further including a capture register 91 instead of the timer counter 8 is provided.

The capture register 91 has a read signal R.
Can be read by the CPU 2 via the bus 4 in synchronism with the above.

Next, the operation of the second conventional microcomputer will be described. Here, except for the capture register 91 of the timer counter 8B, it has the same configuration as the timer counters 7 and 8 in FIG. 4 and the same operation. Therefore, only the differences will be described here. First, the timer counter 7
When the interrupt flag INTT79 of "0 → 1" is set, the count value Nb of the counter 85 is set to the capture register 9
1 and held. The CPU 2 reads the value of the capture register 91 in the interrupt processing routine to obtain the count value of the counted pulse TIb = 0BH.

[0022]

The above-mentioned first conventional microcomputer, when counting the counted pulses input from the outside by the count timer which is one of the built-in timer counters, counts the count value during the counter operation. Since it has to be read, the cycle of the counted pulse has to be equal to or longer than the counter read instruction cycle, and there is a drawback in that high speed is lacking.

Further, the counted pulses are counted in the period from the start of the operation of the count timer to the start of the operation of the time measurement timer, or in the period from the occurrence of the interrupt of the time measurement timer to the start of the reading of the count value of the count timer. However, there is a drawback that the count value becomes inaccurate.

On the other hand, the second conventional microcomputer has a capture register, so that the above-mentioned drawback of lacking in high speed is solved, but the period from the start of operation of the count timer to the start of operation of the time measurement timer is eliminated. The drawback of the inaccurate count value due to the counting of the counted pulses is still left, but the provision of the upper capture register causes a new increase in circuit scale and a cost increase factor.

The object of the present invention is to solve the above drawbacks, to speed up the frequency of the counted pulse, and to count the counted pulse only within a predetermined measurement time to suppress the increase of the circuit scale. To provide a computer.

[0026]

A microcomputer according to the present invention selects any one of a plurality of clock signals having a plurality of frequencies as a selected clock signal and controls the supply of the selected clock signal to obtain a control clock. Clock control means for outputting a signal, counting means for counting the control clock signal and outputting a count value, comparison value setting register means for storing a set value for comparing the count values, the count value and the First and second timer counters each including a comparing means for generating a coincidence signal corresponding to the coincidence with the set value, and an output holding means for holding an output signal inverted in response to the supply of the coincidence signal. In a microcomputer provided, at least one of the clock signal control means of the first and second timer counters has the other counter. The output signal of Makaunta is configured to include a control signal input means for inputting as a supply control signal of the selected clock signal.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 4 are designated by common reference characters / numerals, the embodiment of the present invention shown in FIG. Is a frequency divider 1 and a CPU 2 which are common to the conventional microcomputer.
In addition to the ROM 3, the bus 4, the signal lines 5 and 6, the timer counter 7, a timer counter 8A including a 3-input AND gate 83A instead of the timer counter 8 is provided.

The added third input terminal of the AND gate 83A is connected to the output terminal T2 and supplied with the output signal O.

Next, the operation of this embodiment will be described with reference to FIG. 1. First, the F / F 78 of the timer counter 7 will be described.
Becomes "1" by writing "1" as the setting data Da into the operation control circuit 70, and when the count pulse Pa is supplied during the output of the coincidence signal Ca from the comparison circuit 77, its output O Is reversed. This output O is output terminal T2 and AND gate 83A of timer counter 8A.
Is supplied to.

The AND gate 83A, in addition to the output O,
In response to the supply of the output clock X of the MPX 81 and the output data Db of the operation control circuit 80, AND operation of these data is performed and the count pulse Pb is output to the counter 85.

Next, as in the conventional case, the timer counters 7, 8 are
Each of A is a time measurement timer and a count timer, and the counting operation of the externally input counted pulse of the microcomputer of the present embodiment will be described with reference to FIG. 2 showing the operation time chart. The operation modes of the timer counters 7 and 8A are set.

Next, the operation of each of the timer counters 7 and 8A is started. First, the CPU 2 sets “1” as the data Da to the operation control circuit 70 via the bus 4 according to the program (command) IP of the ROM 3. At this time, the counter 75 is initialized to '00H' and F / F7
8 and INTT79 are "1" and "0", respectively. At this time, the output O which is one of the input signals of the AND gate 83A of the timer counter 8A becomes "1", so that the counter 85 sets the set value Mb (FFH) of the comparison value constant register 86.
The counted pulse T input from the terminal T3 until
It counts up in synchronization with Ib.

After setting “1” as the data Da, the counter 75 sets the set value Ma of the comparison value setting register 76.
The count-up is performed in synchronization with the count pulse Pa corresponding to the clock Xa until it coincides with'n '. Counter 75
The counter 75 rises to the initial value "00H" at the rising of the next count pulse when "n" becomes "n", and the F / F78 is inverted to "0". At this time, INTT79 is "1"
And generate an interrupt. Then, AND gate 83A
Since the output O, which is one of the three inputs of, becomes "0",
The counter 85 stops counting even when the counted pulse TIb is input. The occurrence of an interrupt due to the INTT79 set is transmitted to the CPU 2, the CPU 2 performs an interrupt process, clears the INTT 79, and executes the INTTa interrupt process routine of the ROM 3. In the INTTa interrupt processing routine, the CPU 2 causes the count value Nb of the counter 85 whose operation is stopped to be Nb.
By performing the reading of, the count value of the counted pulse TIb = 08H is obtained.

As described above, the period during which the output O of the F / F 78 is "1" from the start of the operation of the timer counter 7 which is the time measurement timer to the occurrence of the INTT 79 is the measurement time, and this output O is " Only during the period of 1 ', the timer counter 8A, which is a count timer, counts the counted pulse TIb.
To count.

Next, referring to FIG. 3, in which the same components as those of FIG. 1 according to the second embodiment of the present invention are designated by common reference characters / numerals and shown in the same block, the present embodiment shown in FIG. The difference of the above-described first embodiment from the example is that a timer counter 7A including a 3-input MPX 71A corresponding to an external clock TIa input from an input terminal T5 is provided instead of the timer counter 7.

The MPX 71A has clocks Xa1 and Xa similar to the MPX 81 of the timer counter 8A of the first embodiment.
CL out of 3 clocks of 2 and external clock TIa
One of them is output to the AND gate 73 according to the output signal of the SEL 72.

Timer counter 7A which is a time measuring timer
By selecting the clock TIa as the clock Xa output from the MPX 71A with the CLSEL 72, a count pulse can be supplied from a clock source such as another microcomputer operating externally, so that the selection range of time measurement is widened.

As described above, the microcomputer of this embodiment has the advantage that it can achieve the same purpose as that of the first embodiment and that the selection range of the measurement time of the clock measurement timer becomes wider.

[0039]

As described above, in the microcomputer of the present invention, the clock signal control means of one count timer of the timer counter selects the output signal of the other timer counter, which is the time measuring timer, to control the supply of the clock signal. By providing the control signal input means for inputting as a signal, when the counted timer from the outside is counted by the count timer, it is not necessary to read the count value during the counter operation, so that the frequency of the counted pulse is set high. It has the effect of speeding up.

Further, the counted pulses are counted in the period from the start of the operation of the count timer to the start of the operation of the time measurement timer, or in the period from the occurrence of the interrupt of the time measurement timer to the start of the reading of the count value of the count timer. Since it is eliminated, there is an effect that an accurate count value can always be obtained.

Further, since it is not necessary to add a capture register or the like, there is an effect that factors that increase the circuit scale and cost are eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a microcomputer of the present invention.

FIG. 2 is a time chart showing an example of the operation of the microcomputer of this embodiment.

FIG. 3 is a block diagram showing a second embodiment of the microcomputer of the present invention.

FIG. 4 is a block diagram showing a first conventional microcomputer.

FIG. 5 is a time chart showing an example of the operation of the conventional first microcomputer.

FIG. 6 is a block diagram showing a second conventional microcomputer.

[Explanation of symbols]

 1 frequency divider 2 CPU 3 ROM 4-6 bus 7, 7A, 8, 8A, 8B timer counter 70, 80 operation control circuit 71, 71A, 81 MPX 72, 82 CLSEL 73, 83, 83A AND gate 74, 84 OR Gate 75,85 Counter 76,86 Comparison circuit 77,87 Comparison value setting register 78,88 F / F 79,89 INTT 91 Capture register

Claims (3)

[Claims] 1. A clock control means for selecting any one of a plurality of clock signals of a plurality of frequencies as a selected clock signal, controlling the supply of the selected clock signal, and outputting a control clock signal, and the control. Counting means for counting a clock signal and outputting a count value, comparison value setting register means for storing a set value for comparing the count values, and a match signal corresponding to the match between the count value and the set value In a microcomputer having first and second timer counters respectively including an output holding unit that holds an output signal that is inverted in response to the supply of the coincidence signal, and at least the first and second timer counters. The clock signal control means of one of the two timer counters outputs the output signal of the other timer counter to the selected clock signal. Microcomputer, characterized in that it comprises a control signal input means for inputting as a supply control signal. 2. The first timer counter is a time measuring timer for measuring a time from the start of supply of the control clock signal to the generation of the coincidence signal and generating a gate for a predetermined time, and the second timer counter is A pulse count timer that counts the counted pulses input from the outside during the duration of the time gate, and the control signal input means of the second timer counter controls the supply signal of the output signal of the first timer counter. 2. The microcomputer according to claim 1, further comprising a logic circuit for inputting as a signal. 3. The clock signal control circuit of at least the first timer counter comprises an external clock input terminal for inputting an external clock signal from an external clock signal source as one of the plurality of clock signals. The microcomputer according to claim 2.