SU1383327A1 - Device for delaying digital information - Google Patents

Abstract

This invention relates to computing and can be used in digital information delay blocks. The purpose of the invention is to increase the reliability of information delayed by the device. The device contains input 1 and output 8 registers, the first 2 and second 9 buffer registers, the register 3 signs, the first 4 and second 11 readers, the address generator 6, memory block 7, first 5, second 10 and third 12 comparison blocks. The device makes it possible to distinguish a significant distortion of the information words of the delayed array, leading to a change in the previously calculated (before writing to the memory block) indicative information that uniquely determines the rate of change of the function that this array represents. The discrepancy between the signs, calculated before and after the delay, indicates an unacceptable distortion of information. 1 il. with S (L

Description

13

W MS

J5

OO 00

OO from th

com, computed for the same word before writing it into memory block 7.

During normal operation of the device or with a slight distortion of the word (distortion of the least significant bits), the signs calculated before writing and after reading the word are the same, and the logical "O" signal is held at the output of block 12 If, in the course of the delay, there is a significant distortion of the information word (a distortion of the Invention relates to computing technology and can be used in the delay blocks of digital information.

The purpose of the invention is to increase the reliability of information delayed by the device.

The drawing shows a block diagram of a device for delaying digital information.

The device contains an input register 1, the first buffer register 2, the register 3 recognition of its most significant bits), which is the driver, the first calculator 4, the first block 5 tends to go to one side or another of the comparison, the address generator 6, block 7 through the threshold boundary of the rate of change of memory, output register 8, the second buffer function (value difference module, this register 9, second block 10 of the comparative and previous words), then the output

Nor, the second subtractor 11, the third block 12 from the block 12 appears the logical signal "1, the comparison, the input 13 of synchronization, information indicating a large error

14, information output 15, output 16 "Invalid information.

The device works as follows.

At the initial moment of time, all device registers are reset. 20 Zeroing chains are not shown conventionally. Next, the information input of the information word starts to arrive at the information input 14 of the device, thereby increasing the reliability of the information output.

Claims (1)

Invention Formula A device for delaying digital information, comprising an input register, an address generator, a memory block and an output register, the input register input being the information input of the device, the output of the input register connected to the information input of the memory block whose address input is connected to the output lasing array, followed by a square wave sync at the input 13 of the device sync. Moreover, during the first half of the clock, information is read from the memory cell of block 7, the address of which is set by the resuser 6, and during the second half of the clock, for 25 A device for delaying digital information, comprising an input register, an address generator, a memory block and an output register, the input register input being the information input of the device, the output of the input register connected to the information input of the memory block whose address input is connected to the output the new word in this memory cell, the Former addresser, the information The information received at the input of the device and the information read from block 7 are recorded, respectively, in input 1 and output 8 registers on the falling edge of the clock at input 13. the outputs of the memory unit are connected to the inputs of the information bits of the output register, the outputs of the information bits of which are the information outputs of the device, the synchronization inputs of the input and The delay of the set of words is determined by the coefficient of the output registers are connected and are the conversion factor included in the device's synchronization input, which is distinguished by the fact that, in order to increase the reliability of the information delayed by the device, the next information word of the delayed array is written in block 7 together with the corresponding attribute, the second calculator is 40, the first, second and third ones determine whether the comparison blocks exceed the difference, the input of the synchronizer and the previous words of the address generator, the synchronization inputs of the first and second buffer registers and the read / write input the memory unit is connected to the synchronization input of the comparator unit 5. If the difference between the data is 5, the output of the input register of the subconnecting and previous words of the array is connected to the information input of the first buffer register and the first input of the first subtractor, the second input of which is connected the first and second buffer registers are entered into it, the register of the sign, the first and of this and previous words, a certain threshold value, which is stored in register 3. The characteristic is calculated using the subtractor 4 and the first the bit does not exceed the threshold value, then the output of block 5 is set to a logical signal "O if a threshold value was exceeded, then the output of block 5 is a logical signal" 1. Similarly, the attribute is calculated for the main information bits of the word read from block 7 to the output register 8. The calculation is performed using 50 with the output of the first buffer register, the outputs of the first and second subtractors are connected respectively to the first inputs of the first and second comparison blocks, the second inputs — which are connected to the output of the register of the sign, the output of the first comparison block is connected to the control input SHYC1 of the buffer register 9, the subtractor 11 and 55 of the block memory, the control output of the unit 10 comparison. The symptom computed — connected to the input of the test bit — is detected for the delayed information output register; the outputs of the information words are compared in block 12 with the sign bits of the output register connected com, computed for the same word before writing it into memory block 7. During normal operation of the device or with a slight distortion of the word (distortion of the least significant bits), the signs calculated before writing and after reading the word are the same, and the logical "O" signal is held at the output of block 12 If, in the course of the delay, a significant distortion of the information word (distortion, its higher bits) occurred, which leads to a transition to one side or another through the boundary of the threshold for the rate of change of the function (the modulus of the difference in the values of danblock 12 appears as a logical signal indicative of large error this information word, thereby increasing the reliability of the information issued. Invention Formula 20 25 A device for delaying digital information, comprising an input register, an address generator, a memory block and an output register, the input register input being the information input of the device, the output of the input register connected to the information input of the memory block whose address input is connected to the output  sr Shaper addresses information information delayed by the device the second calculator, the first, second and third comparison blocks, with the synchronization input of the address generator, the synchronization inputs of it, the first and second buffer registers, the register of the feature, the first and with the output of the first buffer register, the outputs of the first and second subtractors are connected respectively to the first inputs of the first and second comparison blocks, the second inputs — which are connected to the output of the sign register, the output of the first comparison block is connected to the control input of the memory block, the control output of which is connected to the input test bit size is 1383327 34 the information inputs of the second buffer-control bit of the output register register and the first input are connected to the first and second subtractors respectively, the second input of which is connected to the inputs of the third comparison unit with the output of the second buffer register whose output is the output of the second output unit and output the trusted device information.