SU1376092A1 - Device for interfacing computer with external device - Google Patents

Abstract

The invention relates to computing and can, in particular, be used for transmitting control signals from a computer to external devices and input information from external devices to a computer. The aim of the invention is to increase speed. The device contains two receivers, two transmitters, a control node, a switch, two registers. 1 hp ff, 2 ill.

Description

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The invention relates to computing and can be used to transmit control signals from electronic computers to external devices and to input information from external devices to electronic computers.

The purpose of the invention is to increase speed by increasing the speed of information input.

Figure 1 shows the block diagram of the device) Figure 2 shows the block diagram of the control unit.

The device for interfacing a computer with an external device contains (FIG. 1) the first receiver 1, the switch 2, the second register 3, the first register 4, the second transmitter 5, the control unit 6, the second receiver 7, the first transmitter 8 ..

The control unit 6 contains (FIG. 2) a decoder 9, the first element AND 10, the second element OR 11, the second element AND 12, the third element III 13, the pulse generator 1A, the third element AND 15, the first counter 16, the second counter 17 , first element OR 18, trigger 19

The device works as follows.

First, a command is received to the decoder 9 via the computer control bus, corresponding to the output of information from the computer. At this command, the decoder 9 selects a signal 1 at the first output, which opens the first receiver 1 and the first element AND 10 of the control unit 6, and a signal O at its second output, which goes to the fourth and second outputs of the control unit 6 and closes the second receiver 7 and the first transmitter 8. Next, on the first sync bus output, a sync signal appears, signaling that a computer has loaded the first byte of information on the computer's output bus. This clock signal is simultaneously posted to the first input of the second element OR 11, to the seventh output of the control unit 6 and to the first input of the first element OR 18. In accordance with this signal, the control unit 6 with its seventh output switches the second register 3 to parallel recording of information from the output group switch 2, with its eighth output, provides information from the switch 2 to it. The clock signal arriving at the first OR-18 element passes it and enters the

a single input of trigger 19, which is set to one state, thereby opening the third element 15, through which clock pulses from the generator of 14 pulses start to flow to the counter input of the first counter 16 (eight-bit), to the counter input of the second counter 17, bit whose ratio corresponds to the required number of bits dl. control external devices, as well as open the first element I 10 and close the second element I 12.

By the time of the appearance of the clock pulses at the output of the first element I 10 of the clock signal at the first output of the synchronization bus, the computer is removed, the second register 3 is switched to the sequential read mode and the eighth output of the control unit 6 via the second element OR 11 , according to which the information from the second register 3 is sequentially detected and written into the first register 4. The first counter 16 counts eight clock pulses, zeroes and sets the trigger 19 to the zero state, as a result of which the third element AND 15 is closed and the clock pulses cease to flow to the eighth output of the control unit 6. Consequently, only the first byte of information is recorded in the first register 4 and is stored in it. The number of issued clock pulses is stored in the second counter 17. At the same time, from the output of the first counter 16, a sync signal is received from the output of the computer's synchronization bus, which signals reception of the first byte of information from the computer. Having received this signal, the computer sets the second byte on the output bus and again, on the first synchronization output of the computer, outputs the clock signal and the described cycle repeats again until the end of the recording in the first register 4 of the second byte. Then, the described procedure is repeated until the first register 4 is full. After filling the first register 4, the signal from the output of the second counter 17 is sent to the third B1 input of the control unit 6, through which the second transmitter 5 opens and passes in parallel

view information on the inputs of external devices.

After that, the computer goes into the information input mode from external devices, for which a corresponding command is set up on the computer control bus, which goes to the decoder 9. On this command, the decoder 9 sends signal 1 to its second output, which passes through a quarter and the second outputs of the control unit 6 and opens, respectively, the second receiver 7 and the first transmitter 8.

The same signal unit at the second output of the decoder 9 opens the second element AND 12 of the control unit 6 and sets the second counter 17 to zero, thereby removing the signal from the third output of the control unit 6, therefore closing the second transmitter 5.

 In addition, the decoder 9 inserts

At the first output, a signal O, which arrives at the first output of the control unit 6 and closes the first receiver 1. Then, at the output of the external devices synchronization signal appears, indicating that information on the external outputs of the external devices has information in parallel form, which through the open second the receiver 7 is fed to the parallel inputs of the first register 4. This synchronous signal simultaneously arrives at the first input of the third element OR 13, at the fifth output of the control unit 6 and at the third input of the first element OR 18. In accordance with this signal, the CBOHM control unit 6 with the fifth output switches the first register 4 to the parallel recording of information from the output group of the second receiver 7, with its sixth output, records information from the second receiver 7 into it. Sync signal, actions on the first element OR 18 , passes it and enters the single input of the trigger 19, which is set to one, thereby opening the third element 15, through which clock pulses start to flow from the pulse generator 14 to the input of the first Notebook 16 (eight-bit) and open the second element I 12, as well as the first element I 10 closed by the signal from the first output of the decoder 9 and on the second counter 1 7 by the signal from the second output of the decoder 9.

By the time of the appearance of the clock pulses at the output of the second element I 12, the synchronization signal at the output of the synchronization of external devices is removed, the first register is transferred to the sixth output of the control node 6 through the third element OR 13 by the fourth element 4 of the control unit 6. according to which the information is byte-byte from the first register 4 is sequentially detected and written into the second register 3. The first counter 16 counts eight clock pulses, zeroes and sets t the rigger 19 is in the zero state, as a result of which the third element 15 is closed and the clock pulses stop arriving at the sixth output of the control unit 6. Consequently, in the second register 3, only the first byte of information from the first register 4 is recorded. At the same time, from the output of the first counter 16, a sync signal is received to the input of the computer's synchronization bus, which signals reception from the external devices of the first byte of information. Simultaneously with it, through the open first transmitter 8, the first byte of information in parallel form goes to the computer input bus. Having received this signal and having received the first byte of information, the computer outputs a sync signal at the second synchronization output of the computer, which arrives at the second input of the first element OR 18. With this signal, the described cycle repeats and the control unit 6 activates at its sixth output eight clock pulses and The second register 3 records the second byte of information. Again, the control node 6, from the output of the first counter 16, sends a clock signal to the input of the computer synchronization bus and the second byte of information enters the computer. The described procedure is repeated until all the information from the external devices has been entered into the computer.

Claims (2)

1. A device for interfacing a computer with an external device, comprising two receivers, two transmitters, a switch, a first register, a control node, and a group of information inputs the first receiver and the group of information outputs of the first transmitter form a group of inputs and a group of outputs of the device for connecting, respectively, to groups of information outputs and computer inputs, a group of information outputs of the second transmitter and a group of information inputs of the second receiver form a group of outputs respectively, to the groups of information inputs and outputs of the external device, the group of inputs of the logical condition of the control node forms a group of device inputs for connecting to a group of address outputs of a computer, a group of sync-outputs of a control node forms a group of inputs-outputs of a device for connecting to a group of sync-inputs of a computer, the synchronous input of a control node is an input of a device for connecting an external device to a sync output of the device, the first, second , the third 25 dark entrance of the first element OR and the fourth outputs of the control unit are connected to the enabling inputs of the first receiver, transmitter and second receiver, transmitter, first and second group, respectively, by the information of the control node, the second output of the first receiver are connected respectively to the first and: second groups of information inputs of the switch, the data inputs of the second transmitter are connected to the group of information outputs of the first register, the group of information inputs of which is connected to the group of information outputs of the second receiver, the input of the record-recorder and the clock input of the first register are connected respectively to the fifth and sixth outputs of the control node “2ni, differing so that, in order to improve speed, the Negro is put into The second register, with this group of information inputs of the first transmitter and a group of information outputs of the switch, are connected respectively to groups of parallel information outputs and inputs of the second register, the serial information inputs and output of which are connected respectively to information outputs ™ and the inputs of the first register, the entry of the write-out and the clock input of the second register are connected respectively to the seventh and eighth outputs of the control unit., 2. The device according to claim 1, characterized in that the control node contains a decoder, a pulse generator, two counters, a trigger, three AND elements, three OR elements, the group of information inputs of the decoder form a group of inputs of the logical conditions of the control node, the first input of the first element OR, connected to the first input of the second element OR and the seventh output of the control unit, the second input of the first element OR, the output of the first counter, connected to the zero input of the trigger and the installation input of the first counter, form xp input-output control node, the first input of the third element OR is connected to the three is the synchronous input and the fifth output of the control node, the first output of the decoder is connected to the first input of the first element AND, and is the first d 5 the decoder is connected to the first input of the second element AND, to the installation input of the second counter and is the second and fourth outputs of the control unit, the output of the second and third OR elements are the eighth and juiecTbw outputs of the control node, respectively, the output of the second counter is the third output of the control node, while in the control unit the second input of the third element OR is connected to the output of the second element And, the second input of which is connected to the counting inputs of the first and second counters, with the output of the third element And and the second the first input of the first element AND, the output of which is connected to the second input of the second OR element, the output of the first OR element is connected to a single trigger input, the output of which is connected to the First input of the third And element, the second input of which is connected to the output of the pulse generator. Phage.2