SU1374213A1 - Controlled pulse distributor - Google Patents

Abstract

The invention relates to digital technology, in particular to devices for distributing clock pulses. The aim of the invention is to increase reliability by stabilizing the duration of the output pulses. A distinctive feature of the distributor is that it ensures the duration of the output pulses, which is equal to the duration of the clock pulses, eliminates the appearance of two or more output pulses during one clock pulse and thus allows to remove the restriction on their duration. 1.tab., 1 Il. 9 (L oo 4; 1chE OO y | and and t t F / 1, GB

Description

The invention relates to digital technology, in particular to devices for distributing clock pulses.

The aim of the invention is to increase reliability by stabilizing the duration of the output impulses.

The flow chart of the controlled pulse distributor is shown in the drawing.

The distributor contains triggers 1-3, clock inputs 4 distributors, input 5 of the initial installation, a group of 6 inputs specifying the sequence of pulses of the distributor, outputs 7-9 of the distributor, register 10, elements 11-13, elements NAND 14-19, elements AND 20-22, elements OR 23-25, entry resolution 26.

The control valve operates as follows.

The control code, which determines the order of the impulses at the outputs 7-9 of the distributor, is entered at the inputs b in the register 10. The correspondence between the control codes and the sequences of the appearance of the pulses at the outputs 7-9 is presented in the table.

Control code

Output Pulse Sequence

0o

oo

og

1o

eleven

eleven

7,8,9

8,7,9

7,9,8

8,9,7

9,7,8 9, 8,7

Consider the case when control code 100. The initial setup signal applied to input 5 sets triggers 1–3 to one. The signals 1 from the outputs of the elements OR 23-25 allow the passage of clock pulses from the input 4 through the elements 11-13. The elements AND-NOT 14-19, register 10, and elements 20-22 provide the sequence of pulses given by the control code at the outputs 7-9 of the distributor. At code 100, the first impulse passes

Q

five

0

five

0

five

0

five

output 8. This pulse sets trigger 2 to the zero state. However, signal 1 from the output of the element OR 24 ensures the presence of a signal at the output of the element 12 before the end of the clock pulse at input 4. Only after this does the output pulse terminate. The next clock pulse passes to the outputs of the elements 11 and 13 and to output 7; the third clock pulse goes to exit 9.

Therefore, with control code 100, pulses appear sequentially at outputs 8, 7, 9. To change the sequence of output pulses, it is necessary to change the control code. With other control codes; Neither the distributor works as described above.

Claims (1)

Invention Formula A controlled pulse distributor containing three flip-flops, six AND-NES elements, six AND elements, a register, the single inputs of the first, second and third triggers are combined and connected to the input of the initial installation of the device, the output of the first And element is connected to the first input of the fourth And element , the first input of the first element AND-NOT, the first input of the second element AND-NOT, the output of which is connected to the first input of the fifth element AND, the second input of which is connected to the output of the third element AND-NOT, the first input of which is connected to the output of the second element AND, the first input of the sixth element AND and the first input of the fourth element AND-NOT, the output of which is connected to the second input of the fourth element AND, the third input of which is connected to the output of the fifth element AND-NOT, the first input of which is connected to the output of the third element And, the first input of the sixth element is NAND, the third input of the fifth element AND, the output of which is connected to the zero input of the third trigger and is the first output of the distributor, the second output of which is connected to the output of the sixth element AND, zero input the first trigger, the zero input of the first trigger is connected to the output of the fourth AND element, and is the third output of the distributor, the inverse outputs the first, second and third bits of the register are connected to the second inputs of the first, second and third elements of the NAND, respectively; the forward outputs of the first, second and third bits of the register are connected to the second inputs of the fourth, fifth and sixth elements, respectively -NON, - the outputs of the first and sixth elements AND-NOT are connected respectively to the second and third inputs of the sixth element AND, the information inputs of the first, second and third bits of the register are the first, second and third inputs of the sequence of the distributor pulses, the enable inputs of the first, second and third trigger records are combined and connected to the enable input records of the distributor, the clock input of the distributor is connected to the first inputs of the first, second and third elements I, so that, in order to increase reliability by stabilizing the duration of the output 11 pulses, three elements are introduced into it OR , the outputs of the fourth, fifth, and sixth elements AND are connected to the first inputs of the first, second, and third elements of OR, respectively, whose outputs are connected to the first inputs of the first, second, and third elements, respectively, of the first, second, and third it triggers are connected to second inputs of respective first, second and third elements, OR.