SU1367163A1 - Binary serial code to unit-counting code converter - Google Patents

Abstract

The invention relates to the field of automation and digital computing and can be used in the construction of monitoring and control devices. The aim of the invention is to provide the possibility of converting forward and supplemental codes and increasing speed. The goal is achieved by the fact that a serial binary code to a pulse-pulse code containing a pulse generator 3, a shift register 5, a counter 7, the element AND 1, the element EXCLUSIVE OR 2, the element 4 delay, the element OR 6. 1 or . S (l

Description

00

3i

(35 O9

The invention relates to automation and computing and can be used in the construction of analog-to-digital converters and, in particular, in control devices and recording control programs for CNC machines.

The purpose of the invention is the expansion

yes the output of the converter passes a number of pulses equal to the numerical equivalent of the input number. The overflow impulse according to the installation R-B 15 remote control stops the generator 3 impulses.

The parallel-to-pulse-code conversion was carried out simultaneously with the reception of the subsequent input information.

20

25

the class of tasks to be solved, due to the possibility of Q at the output of counter 7, the transformation of both forward and additional codes, as well as an increase in speed, appear.

The drawing shows a block diagram of a pushed converter.

In the drawing, the following notation is accepted: element AND 1, element 2 of the IC-CLO SHOWTING IL, generator 3 pulses, element 4-delay, shift register 5, element OR 6, counter 7, input 8 characters, information input 9, clock input 10 , write output 11, converter output 12.

The Converter operates as follows.

Before the converter starts operation, the 3-pulse generator is reset to its initial state via the R input (the corresponding circuit is not indicated). Information input 9 receives an input serial two-digit code, and input input 8 characters a character code. From the output of element 2, the EXCLUSIVE OR code goes to the information input of the shift register 5. The pulses arriving at input 10 to the clock C input of the register 5 write the input code to the register 5, the positive number being written to the register 5 as a reverse code, and negative number - in the form of additional. A pulse at the input 11 of the record, which arrives after the n-th clock pulse to the Y input of counter 7, the code from the Q outputs of the shift register 5 is parallelly rewritten to counter 7, the input starts the generator of 3 pulses and adds one to counter 7 element30

35

40

45

Claims (1)

Formula invented The converter follows the binary code into a pulse number code containing a shift register counter, a pulse generator whose R is connected to the output of the counter transfer, and the output of the pulse generator is the output that converts the clock input of which is connected to the clock input of the shift register, which differs , in order to expand the class of solved tasks due to the possibility of the formation of both direct and subcodes, as well as increase the speed, the EXCLUSIVE OR element, the AND element, the delay element, t OR, the output of which is connected to the counting input of the counter, whose recording input with the recording input will convert the first input of the AND element and the S input of the pulse generator, the output connected to the first input of the OR element, the second input of which through the delay element is connected to the output And, the second input of which is co-connected with the input of the converter sign and the first input of the element EXCLUSIVE OR, the second input of which is connected with the information input of the conversion, and the output of the element EXCLUSIVE 50 com and 1, delay 4 and OR 6, if the element AND 1 is open at the second input, i.e. at the input of 8 characters, the level corresponding to 1. Adding one to the contents of counter 7 occurs if the code -1 55 at the input of the converter is connected to the information input of a false number, while the reverse shift register, the bit output code recorded in counter 7 converted to optional. So ( A serial binary code to a pulse code code containing a shift register, a counter, a pulse generator whose R input is connected to the transfer output of a counter, and the output of a pulse generator is the output of a converter whose clock input is connected to a shift register register input, differing in that, in order to expand the class of problems to be solved due to the possibility of converting both direct and additional codes, as well as to increase the speed, the EXCLUSIVE IL element is introduced into it And, the element And, the delay element, the element OR, the output of which is connected to the counting input of the counter, the recording input of which is connected to the recording input of the converter, the first input of the element And and the S input of the pulse generator, the output of which is connected to the first input of the element OR, the second the input of which is connected via the delay element to the output of the AND element, the second input of which is connected to the input of the converter sign and the first input of the EXCLUSIVE OR element, the second input of which is connected to the information input of the converter, and the output of the IC element KEY OR which are connected to the bit inputs of the counter. Thus, both positive and negative numbers are represented in counter 7 by an additional code. The pulses from the output of the generator 3 arrive in the form of a number-pulse code at the output 12 of the converter and, through the element OR 6, to the counting C input of the counter 7. The overflow pulse P. P when the output of the converter passes a number of pulses equal to the numerical equivalent of the input number. The overflow pulse according to the setting R-BXO-DU stops the generator of 3 pulses. The parallel code is converted into a pulse number code simultaneously with the reception of subsequent input information. at the output of counter 7 appears, connected to the information input of the shift register, bit outputs Claims of a serial binary code converter to a pulse code code containing a shift register, a counter, a pulse generator whose R input is connected to the transfer output, a counter, and the output of the pulse generator is the output of the converter whose clock input is connected to the shift clock input - register, characterized in that, with the aim of expanding the class of tasks due to the possibility of converting both direct and additional codes, as well as speeding up, it is entered EXCLUSIVE OR element, AND element, delay element, OR element, the output of which is connected to the counter input of the counter, the record input of which is connected to the converter record input, the first input of the AND element and S input of the pulse generator, the output of which is connected to the first input of the OR element the second input of which is connected via the delay element to the output of the AND element, the second input of which is connected to the input of the converter sign and the first input of the EXCLUSIVE OR element, the second input of which is connected to the information input of the converter l, and the output element is EXCLUSIVE OR connected to the information input of the shift register, bit outputs which are connected to the bit inputs of the counter.