SU1309316A1 - Parallel n-digit code-to-sequential code converter - Google Patents

Abstract

The invention relates to computing and can be used in data transmission systems to convert parallel code to serial. The aim of the invention is to improve the speed of the device. The device contains shift registers 1 and 2 of n + 1, block 3 for selecting the most significant unit, element OR 4, generator 5 clock pulses, switch 6, information inputs 7, information output 8, control outputs 9 and 10, setup input 11 devices. 1 il. SAE about CO WITH O)

Description

one

The invention relates to computing and can be used in data transmission systems for converting parallel code to serial.

The purpose of the invention is to increase the speed of the device.

The drawing shows a diagram of the Converter.

The device contains registers 1 and O 2 of a shift of n + 1, block 3 in the upper unit, element OR 4, generator 5 clock pulses, switch 6, information inputs 75 information output 8, control outputs 9 and 10, setup input 11 devices.

The block 3 in the upper-most significant unit can be executed in the form of a n-bit register, the information inputs of which are connected to the inputs of the block, the installation input - to the installation input of the block and the discharge elements AND, whose codes are connected to the outputs of the block, the first the inputs are connected to the direct output of the corresponding bit, and the rest to the inverse outputs of the higher bits.

The converter works as follows.

Before the start of operation, the initial installation of the converter takes place via the installation input 11, and the shift registers 1 and 2 and the register of the high-order unit 3 are set to the initial (zero) state. At the output of the high bit of shift register 2, a level O of logic O appears, which prepares the generator 5 clock pulses for operation on a pair of control input. The parallel code to be converted is entered from the information inputs 7–45 in, pa: the first shift register registers 1 and into the register of block 3 of the higher unit. The bits of the code to be converted, the bits of the shift register 1 and the register of block 3 of the upper junction .jO units are combined by the least significant bit. The highest unit of the code to be converted determines the format of the conversion. At the output of block 3, corresponding to the conversion format, a high level appears, which will write 1 to the corresponding bit of the second shift register 2. At the same time, a high level occurred at the output of block 113093162

3 highlight the higher unit, is fed to the input of the element OR 4 and from its output - to the first control input of the generator 5 clock pulses, to start it, and to the control output 10 of the converter, signaling to external circuits about the start of conversion.

In this case, the output bus 8 is connected via the switch 6 to the bit of the shift register 1, which follows the bit containing the highest code unit. The pulses from the generator 5 clock pulses are fed to the shift inputs of the registers 1 and 2 shift. As a result, the recorded information is shifted in shift register 1 and sent to output 8 of the converter through the selected input of switch 6. Simultaneously shift 1 is written to the corresponding bit of the second shift register 2. Information is output to the converter output until 1, recorded in the shift register 2, advances to the high order. At phenomenon 1, the high level of the shift register 2 at the control output 9 of the converter appears high which closes the generator of 5 clock pulses at the second control input and signals to external circuits that the conversion is complete.

Claims (1)

35 claims A parallel n-bit code to serial converter that contains shift registers (p − 1), the reset inputs of which are combined and connected to the device reset input, the information inputs of the lower bits of the first shift register are the information inputs of the device, and the h outputs the higher bits are connected to the corresponding scm inputs of the switch, the output of which is the information output of the device, the clock generator, the output of which is connected to the input of the shift of the first shift register, and the element m OR, whose output is connected to the first control input of the clock and is the first control output of the apparatus, characterized in that, in order povshgeni operating speed of the device, it entered unit vschedeni oldest unit of information .- 30 313093164 The input inputs of which are connected to the bit of the second shift register, the corresponding information input input of the higher bit of which is a device, the reset input is connected with the keys to the second control input of the device reset input, the i-th output of the clock pulse and the high-voltage output unit ( i 5ts with the second control output of the set- 1 ... n) is connected to the 1st control unit, the shift input of the second register-input switch, with the i-th input of the shift elec- tor is connected to the output of the generator OR or record (n-1 + 1) -Totor cycle new impulses.