SU1327317A1 - Multichannel demodulator of discrete signals - Google Patents

Abstract

Invention m. used in multichannel modem receivers. The purpose of the invention is to increase the amount of received information. The device contains an arithmetic unit 1, a constant HHHbrfi storage unit 3 and a sampling unit 4. Counters 2 and 5, the envelope register 6, the current address memory block 7, the buffer storage block 8, the control block 9 are entered into the device. In item 2 of the file, the device of block 1 is given, containing five registers, a code converter, an adder, a multiplier, a driver of control signals. 1 3.p. f-ly. 2 Il. with 00 00 figure 1

Description

The invention relates to communication technology and can be used in multi-channel modem receivers.

The purpose of the invention is to indicate the amount of received information.

FIG. 1 shows a structural electrical circuit of the proposed multi-channel modulator; in fig. 2 is a structural electrical circuit of an arithmetic unit.

The multichannel discrete signal modulator contains the arithmetic unit 1, the first counter 2, the persistent storage unit 3, the sampling unit 4, the second counter 5, the envelope register 6, the current address memory unit 7, the buffer storage unit 8, the control unit 9.

The arithmetic unit contains the first 20 Q reference oscillation, second, third, fourth, and n - The result of the calculation is the registers 10 - 14, code conversion in BZB 8.

The driver 15, the adder 16, the multiplier 17. The operations indicated sequentially the control signal generator 18 are performed on all frequency channels.

Multichannel demodulator discre-25 for one countdown. Calculations

signaling works as follows.

are repeated in each count of the orthogonality interval.

Thus, by the time the orthogonality interval ends in the BZB 8

the third input of the arithmetic unit 1, zo P nts the value of the channel projections

signals that enter the unit

The group signal S arrives at

35

in which at each clock interval it is multiplied by the count of the sinusoidal envelope of the raised cosine F, formed in arithmetic. com block 1 using counter 5 and the Permanent storage unit 3, the introduction of the multiply operation by the envelope count F, or the elimination of this operation, allows you to change the processing mode of the group signal 40, accepting it with low or greater selectivity. The result of the multiplication oi is stored in register 6 of the envelope. This value is cleverness (solution) (unspecified).

From the above it is known that, -F ,,

one

2

where A is the address of reference. Then

Tg g

WITH/

S dtsin Ak)

formed in the following way. The contents of the counter 5 is increased at each counting by one and is fed back to the higher bits.

for lower-order address bits, zeros are given.

The values of sin Aj are fed into the arithmetic unit 1 on register 11,

50

The values of the samples of reference co-5 of the 6th to the 9th) address tires of the PZB 3, swings (sines and cosines), which are stored as binary numbers in the PZB 3 and fed into the arithmetic unit 1, Sample of sines and cosines from the PZB 3, it is carried out according to the previously calculated A-addresses using the sampling block 4, which forms the sign of the sine and cosine reference and the address of the reference oscillation values. The calculation of the current address of the op-e-oscillations over the i-th channel occurs by algebraically adding the address of the previous reference (p-1) stored in block 7 of the current memory

In accordance with the current time reading it, produced in the orthogonality interval, at the output of register 11, the signal has a positive or gg negative value and then goes to the first input of the multiplier 17.

At the second input of the multiplier 17 comes the group signal S, arriving at registers 12 and 13,

addresses, and arriving in the arithmetic unit 1 with the increment of the current address on the i-Nfy channel, which is formed by the counter 2, taking into account the frequencies - „„,

NOI amendments to the arithmetic unit 1,, -f,., (.

The result of the algebraic addition is written in block 7 of the memory of current addresses and in the register of current addresses of block 4 of the sample.

The result of multiplying by the values of the samples of the reference oscillations is added in the arithmetic unit 1 with the propagation of the channel signal to the previous one, received from the buffer storage unit 8. X, "" "Qsin -t- X; (n-1) Y, -, ,, Qcos + Y; (n-1).

35

40

decide (not

From the foregoing it is known, -F ,,

one

2

where A is the address of reference. Then

Tg g

WITH/

S dtsin Ak)

formed in the following way. The contents of the counter 5 is increased at each counting by one and is fed back to the higher bits.

for lower-order address bits, zeros are given.

The values of sin Aj are fed into the arithmetic unit 1 on register 11,

 6th to 9th) address tires PZB 3,

50

5 of the 6th to the 9th) address buses of the PZB 3,

In accordance with the current time reading it, produced in the orthogonality interval, at the output of register 11, the signal has a positive or gg negative value and then goes to the first input of the multiplier 17.

At the second input of the multiplier 17 comes the group signal S, arriving at registers 12 and 13,

31

In multiplier 17, S is multiplied by sin A. The product of the code converter 15 is fed to the first input of the adder 16, the second input of which receives the value of the group signal from register 13 to get the sum S S sin L.

According to the right: y signal O or 1, which is contained in the sign level of the product S-sin A, the output of the code converter 15 passes the direct or inverse value of the signal, respectively.

The signal SiS sin A obtained in the adder 16 needs to be shifted from SiSsinAK into in order to obtain a fading.

This is done through the installation. The signal is taken, starting with the second low-order bit of the adder 16, and is written to the envelope register.

From block 7 of the current address memory, the value of the current address is fed to the adder 16 of the arithmetic block 1.

Counter 2 generates address increments for each channel, since there is a one-to-one correspondence between the channel number and the increment value. The increment of the address enters the adder 16 of the arithmetic unit 1, is summed with the value of the current address and is stored in register 10, then again sent to the adder 16, where it is added to the frequency and total correction to register 14. Aj received in the adder 16 is poured into block 4 of the sample and in block 7 of the memory of current addresses. In block 4 of the sample, the obtained value of A is converted to the address from which 3 reference oscillation values are retrieved from the corresponding samples. Sample block 4 contains an 11-bit register, the 10th and 11th bits of which, in accordance with the value of the current time -utf, determine the square of the selectable sine value.

The magnitude of the reference oscillations at this counting from the PZB 3 enters the multiplier 17. From the envelope register 6, the values d are received. The product of the reference oscillation countdown is sent to the adder 16, where it is added to the projection of the channel signal at the previous counting received from the buffer storage unit 8. From

g

s

0

five

about Q

five

0

five

17

totalizer 16 result is forwarded

in woof, 8.

The demodulator operation control block .9 is a programmable logic control block.

The control signal generator 18 operates on the Start control signals coming from the control unit 9.

Claims (2)

1. A multichannel discrete signal demodulator containing an arithmetic unit, a persistent storage unit and a sampling unit, characterized in that, in order to increase the amount of received information, the envelope register is entered, two counters, a current address memory block, a buffer storage unit and a control unit, the outputs of which are connected to the first inputs of the arithmetic unit, to the inputs of the first and second counters, to the first inputs of the sampling unit, to the envelope register inputs, to the first inputs of the current memory block addresses with the first inputs of the buffer storage unit and with the first inputs of the permanent storage unit, the outputs of which are connected to the outputs of the first counter and to the second inputs of the arithmetic unit whose outputs are connected to the second the inputs of the sampling unit, with the second inputs of the buffer storage unit and with the second inputs of the memory memory address addresses, the outputs of which are connected to the outputs of the envelope register and to the third inputs of the arithmetic unit, the fourth inputs of which are connected to the outputs of the buffer storage unit, while the outputs of the second counter are connected with the second inputs of the permanent storage unit and with the outputs of the sampling unit. 2. A demodulator according to claim 1, characterized in that the arithmetic unit contains five registers, a multiplier, a code converter, a driver of control signals and: an adder, the outputs of which are connected to the inputs of the first register, the outputs of which are connected to the first inputs of the adder, with the outputs code converter with second register outputs and with the first inputs of the multiplier, the second 5132731 Which inputs are connected to the third-register outputs, p. the inputs of the fourth register and the inputs of the third register, the outputs of the fourth register are connected to the outputs of the fifth 5 register and to the second inputs of the adder, the outputs of the multiplier are connected to the inputs of the code converter, the outputs of the control signal generator are sub-closure-. the inputs to the initial installation and 10 the control inputs of the first, second, third, fourth, and fifth registers, while the inputs of the control signal generator, the inputs of the second register, the inputs of the third register, and the inputs of the fifth register are respectively the first, second, third, and fourth inputs of the arithmetic unit whose outputs are the outputs of the adder. .2