SU1163477A1 - Adaptive delta modulator - Google Patents

Abstract

ADAPTIVE DELTA MODULATOR containing a comparator, the first input of which is connected to the input bus, a shift register, the input of which is connected to the output of the comparator, a clock input connected to the clock bus,: the output of the first discharge of the shift register is connected to the output bus and the first input of the main multiplier, the output of which through the integrator is connected to the second input of the comparator, characterized in that, in order to increase the transmission accuracy by increasing the signal-to-noise ratio, an adder and a correlator are entered into it, each of which contains connected in series multiplier and accumulator, the first inputs of multipliers of all correlators are connected to the output of the first bit of the shift register, the second input of the multiplier of each correlator is connected to the output of the corresponding bit of the shift register, starting with the second, accumulators of all correlators are connected to the inputs of the adder, The code (L of which is connected to the second input of the main multiplier, with this number of bits of the shift register is N +1, where M is 3,5,7, .... a 00 4:

Description

The invention relates to computer technology and can be used in the construction of systems for transmitting speech signals through discrete communication channels. 5

The purpose of the invention is to improve the accuracy of transmission by increasing the signal-to-noise ratio.

The drawing shows a block diagram of an adaptive delta modulator. 1®

The input bus 2 and the output of the integrator 3 are connected to the first and second inputs of the comparator 1, the output of the main multiplier 4 is connected to the input of it. The output of the comparator. 15 is connected to the input of the shift register 5, the clock input of which is connected to the clock bus 6, and the output of the first discharge is connected to the first input of the main multiplier 4, to the 20 output bus 7 and to the first inputs of the correlators 8, the second inputs of which are connected to the outputs of the corresponding bits of the register 5 shifts starting from the second. Each correlator 8 contains a multiplier 9 connected in series, the inputs of which are connected to the inputs of the correlator, and a drive 10, the outputs of the drives 10 of all correlators 8 3θ are connected to the inputs of the adder 11, the output of which is to the main correlators of the register register N = 3,5 , 7, ....

connected to the second multiplier 4. The number 8 is N, the number of bit 5 ’shift is N +1, where

The device operates as follows.

The input signal from bus 2 is fed to the first input of comparator 1, on. 40, the second input of which the signal from the output of the integrator 3. The output of the comparator 1, the signal goes to the first input of the shift register 5, the first discharge of which plays the role of ^ 45 amplitude two-level quantizer. With the frequency set by them. pulses arriving at the clock input of shift register 5 from clock bus 6, at the output of the first bit 50 of shift register 5 at time t, a sequence of binary symbols b; is formed, taking values +1 or -1 depending on the sign of the signal at the output of comparator 55 1 and arriving at the output bus 7, the first input of the main multiplier 4 and the first inputs of the multipliers 9 of the correlators 8, formed at the outputs 2, 3,. . . , Ν + 1st digit register-. At the time point 5, the binary symbols b '·, b, ..., are fed to the second inputs of the corresponding multipliers 9 of the correlators 8. The multipliers 9 multiply the binary symbols b / with binary symbols, ·. ., respectively. The output signals of the multipliers 9 go to the inputs of the drives 10. At the outputs of which are formed samples of the correlation function of the signal at the output of the first bit of the shift register at the time according to the formula

·) Where [U = 1, 2 ..

N. - the number of clock intervals t _t <

between binary characters b;

M - the averaging interval, "" UIO "equal to M = ——— 25Ί O ' ^{3 T}

T _T '

N = 3,5,7, ...,

Samples of the correlation function From the outputs of the drives 10 are fed to the inputs of the adder 1 1, the output of which is the signal of the sum of the samples of the correlation function of the output jU = N signal of the delta modulator X | tl «1 which is fed to the second input of the main multiplier 4, as a result of which the pulse amplitude coming to the first input of the main multiplier 4, is measured in such a way that the sum of the samples of the correlation function of the output signal of the _delta-modulator tends to zero. (W-h

Then, for X R · (m) = 0, the ratio / u = 1.

“The signal-to-noise ratio for the decoded signal will be maximum.

Thus, the introduction of correlators and an adder provides an increase in the signal-to-noise ratio at the output of the adaptive delta modulator, thereby increasing the accuracy of message transmission.

Claims (1)

ADAPTIVE DELTA MODULATOR containing a comparator, the first input of which is connected to the input bus, a shift register whose input is connected to the output of the comparator, a clock input is connected to the clock bus, · the output of the first bit of the shift register is connected to the output bus and the first input of the main multiplier, output which is connected through an integrator to the second input of the comparator, characterized in that, in order to increase the transmission accuracy by increasing the signal-to-noise ratio, an adder and up to ⁷ correlator are introduced into it, each of which contains The multiplier and the drive are connected in series, the first inputs of the multipliers of all correlators are connected to the output of the first bit of the shift register, the second input of the multiplier of each correlator is connected to the output of the corresponding bit of the shift register, starting from the second _(the terminals of the drives of all correlators are connected to the inputs of the adder, the output of which is connected to the second input of the main multiplier, while the number of bits of the shift register is N + 1, where N = 3,5,7, .... SU ,,,, 1163477