SU1309221A1 - Method of controlling current at output of bridge transistor inverter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in automation and electric drive systems to convert DC voltage to AC and regulate the load current. The goal is to increase the efficiency and accuracy of current regulation at the inverter output. In the invention, the value and sign of the current at the output of the inverter are measured and compared with a predetermined value and a sign of the current setting signal. Then it is necessary to determine the sign of the difference between the signal of the current setting and the signal proportional to the load current. If a positive difference sign appears, then it is necessary to remove the command to turn on one of the negative current direction transistors and turn on the time delay, after which the command to turn on the mentioned transistor is removed. With a negative difference sign, similar operations are performed with a positive direction transistor, 1 current with allowance for the corresponding time delay. The time delay in the output signal function is adjusted after it is rectified, which reduces the current ripple. 2 hp ff. 2 Il. i (i'm so on)

Description

M: ") ()) scatter refers to e. Yuktrotshpike ii can be nsio.chzovaia in systems of automation and electric drive for converting 15a1,; 1I liocroviiiHoi o ngifu leasing in pemempoe and rcm-ulyarovii load current.

I.le.ib invention - improving the efficiency and accuracy of current control at the output of the inverter.

Fig. 1 shows a diagram of the variation of the 5 output current; FIG. 2 is a functional diagram of the device, realizing its assembly.

VcTi iOHCTBo for regulating the current in the load of the bridge transistor inverter contains an input source 1, the input of which is connected to the inputs of the commander 2-5, the output of the comparator 2 under the key to the solar inverter b and the anode of the diode 7. And the output of the logical inverter 6 is to the dna 8. The cathodes of the diodes 7 and 8 are connected to the nodes 9 and 10 of the time delay (their equals: 1 ju. and inputs 11 and 12, respectively). Comparator 3 pod.1yuchep to the force input 13 of the device 9 time delay, and the output of the comparator |) and 4 - to the force input 14 of the device 10 time delay. Output 15 of the input source I / Ia is also connected, the input of which is subordinate to the local signals of 16 and 17 nodes 9 and 10 of the time delay corresponding to iH TCTiseHHo. Outputs Sews 9 and 10 of the time delay and the comparator 5 are connected to the input of the mms device 18, which controls the bridges and the transistors and the inverter 19, containing transistors 20-23, and the reverse diodes 24-27. In the diagonal of the bridge bridge transistor ineromer ios single, the load circuit 28 and the current sensor 29, the output of which is connected, are connected to the second inputs of the com- pactors 2-4.

The device works as follows.

Suppose that transistors 20 and 23 are open and in a narrow |) narrow current flows in a positive direction. Smaller than the specified value, and oppositely, the EMF of the load E is directed opposite to the current (time variable ti), then the node is affected by the difference ianr is the yarn source voltage and opposite the emf load current increases, while the outputs of comparators 2 and 5 have a positive signal, and commarators 3 and 4 have a negative signal, pa outputs the nodes. 1a 9 time exposure. A single signal, and a node you-. Stand-off time 10 - well; | Evo (time interval h -til). Consider how the current U of the ruler U rises to the preset value {. Moment of time t :)), the error regularly changes its sign, a negative signal appears at the output of com.parator 2, then .1a 9 time delay appears with a zero signal. Through the logic inverter 6, the time delay countdown is started: 1 dashed knot. ym 10 time exposure. On

0

5 0 5 Q 5

0 r 0 5

The inputs of the logic device 18 are established by the combination of the signals, by which it closes one of the most powerful transistors, for example). 23. Then the load is short-circuited through the remaining transistor of resistor 20 and reverse diode 25, and the load current begins to cna; UiTb iodine with counter-emf and short-circuit (time interval). A positive signal is restored on the output of co.parator 2, the time delay of node 10 is canceled, but the time delay of the name of node 9 starts, after opening which a typical signal appears at the output of this device. After that, the transistor 23 is turned on, and the process is repeated, with the only difference that instead of the transistor 23, the transistor 20 can be turned off (the time interval

t: i-t.r,).

Suppose now that the back-EMF of the load is directed in accordance with the load current, and that the initial conditions of the process remain the same (time is Ir,). Then noc.ie of the transfer of the load current through the specified value (time t (i) and lock up the transistor 23, the load current will continue to increase, flowed through the transistor |) 20 and the reverse diode 25 (interval of 1 ti; - t). Therefore, the countdown is timed. Yum 10 is not canceled.

After the end of the countdown at the output of the node I), the time delay -1; and a single signal appears. At the output of the .io-i device 18, a combination of signals is set up, by which the remaining power is turned off. 1 transistor 20 (.time 1-). The load current under the action of the voltage difference of the source of the tapes and the counter-EMF of the load decreases, and the capacitor passes through the reverse diodes 25 and 26 (time interval tj-ts). When the load current reaches the specified value, the error is adjustable. There is a positive signal at the output of komponent 2, and a zero signal at the output of time delay node 10. At the same time, the time delay countdown is started by the node 9 (time interval t "). In this case, the logic device 18 includes one of the transistors 1O.configured.: | Nnogo direction of current, nanoamer transistor 23, and the whole process. Is repeated (and the future. 1Y time ts-1 |.), Till -t | ;.).

If during the reference time of the node time delay 9 and.: | And 10 the time delay of the pei-ulirovapi is out of tolerance, then at the output of the comparator 3 (time points b ;, t | G) or 4 (time moments ti-. 1,}, depending on the sign of the error, a single signal appears, which leads to the formation of the reference time reference. The time-delay nodes 9 or 10 correspond to the same. The process also occurs in the same way with an abrupt change in the output signal source 1 input signal.

Time delay adjustment as a function of the output signal of the input signal is carried out via rectifier 15.

From the analysis performed, it follows that the current pulsations are reduced, Kpl1ve; 1n; chen in relation to the known.

Claims (3)

1. A method of controlling the current at the output of a bridge transistor inverter, HJIH, which measures the value and sign of the current at the output of the inverter and is compared with a given value AND sign of the signal: -, current, characterized in that, in order to increase efficiency and The accuracy of the current current at the inverter output is determined by the sign of the difference between the current setting signal and CHi na.ia. nrc) —corny load current, with the appearance of a positive sign of the difference, remove the command to turn on one O of the negative transistors. In the current direction li vc, the clock countdown time TJ is read, but the end of which removes .chd to turn on the remaining power: - the negative current direction resistor; i put on: 1 current signal includes two current transistors. , and with the negative, the nominal sign of the cis on the current, leaving the current five 0 v; vein | 1H1 1: and the weight of the tranl: stor, with but v. ji-ni of the negative difference sign, was taken by the command iia vk / |; - Horo nolo 1ch1gge. The current is directed to the current and includes the OTC iCT from the Bjic.MejiH end, the end of the otog Ogo command is removed}; m the activation of the remaining transient of the current circuit .1n the current :; ; iipii a negative sign of the signal. setting the current vk: 1.You have two transistors to deny. current, and at a positive sign, the weight of the transistors is left off, 1; if the change in the sign of the difference between the NRO1K goes to the end of the time | or tz, then the countdown data; pulled out time off, turn on the countdown of another time delay, corresponding to a new one and a new difference sign. 2. (duosobnu.n., Differing in terms of Thu;) additionally: what is indicated is the difference, compare it with the preassigned |, threshold value Ln in the case of the difference by the difference of the Hopoi OBoro atomic force difference | Lead time delay. Correspondingly uni1 and a given sign of the difference. 3.Ciiocof) but nn. 1 n 2, defining the bodies; and tj and poro ~ O South values change to a functional signal. setting the current, starting from some 1) minimum value. ag / pu..2