SU1307567A1 - Generator of difference frequency of pulse sequences - Google Patents

Abstract

The invention can be applied in circuits using differential frequency signals, for example, in a phase locked loop. The purpose of the invention is to increase the dismounting ability and increase the speed during device operation, which is achieved by the fact that the first, second and third triggers are executed on // (- triggers included according to the scheme shown in the drawing. The drawing also shows the first input 1, triggers 2, 3 and 4, output nina 5, pulse shaper 6, torus input 7 7. The device is explained in the graphs in the description of the invention. 2 or SS (Ls: X.

Description

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The invention relates to a pulse technique and can be used in circuits using differential frequency signals, in particular in a phase locked loop.

The purpose of the invention is to increase the resolution and increase the speed while simplifying the device.

FIG. 1 shows a diagram of the device; in fig. 2 - time diagrams that show his work.

The device contains the first input I I connected to the clock input of trigger 2 and / -input of trigger 3, the inverse output of trigger 2 is connected to the / -input of trigger 3, and the inverse output of trigger 3 is connected to / -input of trigger 2, / ((- inputs which are connected to a logical source1 0 zero, trigger 4, the / input of which is connected to the forward output of trigger 2, / (—the input is connected to a logical zero source, and the clock input is connected to the first input line 1, the output of the trigger 4 is connected to output bus 5, driver 6 impuls. with two outputs, the first output otorrhea connected to the clock input of flip-flop 3 and / -Log trigger 2, and a second output connected to / -Log trigger 4, 6 input of the second input is connected to the bus 7.

The device works as follows. in a way.

Bus 1 receives short frequency pulses. F (Fig. 2a), and the 7 g bus stops at the frequency F (Fig. 26) with a certain duty ratio Q, for example, equal to 2. It is known that the frequency F is stable, formed from a quartz oscillator, and the frequency F-2 is controlled (and .FI), which is the difference frequency between the frequency of the high-frequency quartz oscillator with the frequency f ;. and a lower frequency of the controlled oscillator / V ,, i.e. / - / V ,, when using the device in a phase locked loop (PLL). This ratio of frequencies in phase 1, e of the phase-locked loop of the frequency part is divided: see the frequency with ibiFvi variable dividing factor in the feedback circuit to compensate for the nonlinearity of the control characteristic of the tunable oscillator and to stabilize the converter ratio of the F.A. range adjustment. At the first output of the former 6, there are pulses with a duration determined by the speed of the element base used {Fig. 2c) formed on the fronts of the frequency F, and at the second output of the rotator b there are pulses formed from the decays of the pulses of the frequency F-2 of the same duration {Fig. 2d). The presence of two sequences at the output of the imaging unit 6, shifted to the 10th phase, is due to the need to eliminate the situation of simultaneous switching of the trigger 4 to the unit

This is the C input and its reset to zero at the I input, at which an error of calculating the difference frequency is possible. This situation has a greater likelihood.

when using the proposed device in the PLL ring, since the input frequencies in this case are mutually correlated. In the initial state, at the outputs of the flip-flops 2, 3 and 4 there are levels of logical zero. First pulse frequency f

(Fig. 2a) does not turn on trigger 2 into a single state {Fig. 2e), and the frequency pulse F2 from the first output bus of the imaging unit (Fig. 2c) resets trigger 2 (Fig. 2c) to the initial zero state on the / -Band. The second pulse of the frequency F switches the trigger 2 to the single state, the second pulse of the frequency F- on the first output bus of the driver 6 resets the trigger 2 to the initial state. Then a situation arises in which there are two pulses of higher frequency F between the two pulses on the first output 1-driver of the generator, when the first pulse switches trigger 2 to one state, which is written to trigger output 4 by the second pulse F of the frequency F, and a reset occurs simultaneously trigger 2 in ex. zero state, and reset trip-4 4 {phi; 2e) is controlled by the impulses of the frequency bg; ia to the second bus ({worm (phase shifted relative to the pulses on the first output of the driver f,;; at the output of the trigger 4, the first impulse of the difference frequency is generated. Pulse times -: the output of flip-flop 4 appears whenever there is a frequency between pulses FZ

two pulses of frequency F appear, and the difference often a is calculated to an accuracy of nonstable. 1.1-: OST; 1 phase of low frequency consumption /%.

Shaper |. frequency pulses of the sequences containing the first input BUS connected to the clock input of the first trigger,. - the input of the second trigger i with the third input of the third trigger, wherein) the output of the first trigger is connected to the information input of the second trigger, and the inverse output of the second trigger connects to the information input of the first trigger, pulse generator, the first output of which is connected to the clock input of the second the trigger and the input of the first trigger, the second output - with the / - inputs: L third About the trigger, the output of which is connected to the output 5, and the input of the pulse shaper ccjB is connected to the second input bus, iovi 11 oazrea ability and great.; -1i

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speed in simplifying the device, the first, second and third triggers are made on // (- triggers, / (- whose inputs are connected to the logical zero bus, / - input of the third trigger connected to the direct output of the first trigger.

FIG. 2

Claims (1)

Claim The generator of the difference frequency of the ampoule sequences containing the first input bus connected to the clock input of the first trigger, // the input of the second trigger and the clock input of the third trigger, while the inverse output of the first trigger is connected to the information input of the second trigger, and the inverse output of the second trigger is connected with the information input of the first trigger, a pulse shaper, the first output of which is connected to the clock input of the second trigger and the R-input of the first trigger, the second output - with // - the third input its trigger, the direct output of which is connected to the output bus, and the input of the pulse shaper is connected to the second input bus, characterized in that, in order to increase the resolution and increase speed while simplifying the device, the first, second and third triggers are made on // (- flip-flops, / (- the inputs of which are connected to the logical zero bus, the / -input of the third trigger is connected to the direct output of the first trigger.