SU1302433A1 - Shift-to-digital converter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to connect analog information sources with a digital computing device. In order to increase the reliability of the converter by increasing the allowable movement speed in the converter containing the exact readout (TO) 1, register 2, the first 4, the second 5, the third 6 and the fourth 7 differentiating elements, the first 8 and the second 9 elements AND, the reversible counter 10, the element ZI-OR is introduced 3. Shaper 1 is cyclically formed n-bit positional binary code N accurate reference value uniquely defining the movement in Np accurate reading range. At the end of each maintenance cycle, code N is stored in register 2. In accordance with the output of the high bit of register 2 and element 3, the entire range of maintenance is divided into four sections. When passing through the full value of the TO code during forward movement, elements 5 and 7 simultaneously produce pulses that coincide on element 9 and arrive: at the summation input of a reversible counter 10. Similarly, during reverse movement, pulses are produced by elements 4 and 6 when crossing the boundary between first and fourth sections. The output pulse of the element And 8 is fed to the subtracting input of the reversible counter 10, in which the coarse count code is formed. Increasing sections 1 and 4 by decreasing the total area 2.3 made it possible to increase the maximum movement speed in such a converter by 6%. 1 il. 1 tab. (L ao 4: CO with

Description

. The invention relates to automation and computing and can be used to connect analog sources of information with a digital computing device.

The aim of the invention is to increase the reliability of the converter by increasing the allowable moving speed of the converter.

The drawing shows the structure of the converter.

The converter contains a precise reference shaper 1, register 2, element ZI-OR 3, first 4, second 5, third 6, and fourth 7 differentiating elements, first 8 and second 9 And elements, and a reversible counter 10.

The Converter operates as follows.

Shaper 1 cyclically generates an exact-position n-bit positional binary code N that uniquely determines the amount of movement in the exact N range.

rm

that At the end of the cycle, the N code is stored in register 2. In accordance with the output signal of the high bit of register 2 and element 3, the entire TO range is divided into four sections according to the table.

1to, i n) o

2Cf N, I NJ 0

0 1

The differentiating elements 4-7 generate pulses when the level of their input signals changes from zero to unity. As a result, when the code N changes from the fourth to the first part,

fO

/five

20

25

thirty

45

50

current, i.e. when going through the full value of the maintenance code. during forward movement, elements 5 and 7 simultaneously produce pulses that coincide on the element 9 and arrive at the sump input of the reversible counter 10.

Similarly, during the reverse movement, the pulses are produced by elements 4 and 6 when crossing the border between the first and fourth sections. The output pulse of the element And 8 is fed to the subtracting input of the reversible counter 10, in which the coarse count code is formed.

Increasing the first and fourth sections by decreasing the total range of sections 2 and 3 allows you to increase the maximum movement speed in such a converter by 25%.

An increase in the number of inputs of the ZI-IPI 3 element makes it possible to equalize the first and fourth quarters with a total area of three, two and increase the allowable movement speed to one third of the TO range during the TO conversion cycle.

Claims (1)

Formula A transducer for displacement into a code containing a precision reference driver, the outputs of which are connected to the inputs of the register, the forward and inverse outputs of the high-order register are connected to the inputs of the first and second differentiating elements, respectively, the outputs of the first and third differentiating elements are connected to the inputs of the first element, And the outputs of the second and fourth differentiating elements are connected to the inputs of the second element AND, the outputs of the first and second elements AND are connected to the inputs of viiitani and summation of the reverse The corresponding counter, respectively, is based on the fact that, in order to increase the reliability of the converter by increasing the permissible displacement velocity, the ZI-OR element is introduced into it, the first group of inputs of which is connected to the forward output of the first and register bits, the second group of inputs - to the outputs of the second and third highest bits of the register, the third group of inputs - to the direct output of the first 313024334 the third and fourth OR outputs are connected to the inputs of the corresponding high-order bits of the register, and the third and fourth outputs are the differential and inverse outputs of the ZI element.