SU1298910A1 - Frequency divider with variable countdown - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and measuring devices. The purpose of the invention is. nor - increase in speed. To achieve the goal, an amplifier 7 is introduced into the device,; n, two-position switches 8.1-8. p. The device also contains a n-dimensional scaling unit 7, p multi-position switches .2-1 - 2-n, input bus 3, element I 4, triggers 5 and 6, output bus 9. Switches 2-1 - 2-p introduced additional fixed contacts, which are connected to the input bus 3. I Il. (L to with 00 with

Description

The invention relates to a pulse technique and can be used in automation and measuring devices.

The purpose of the invention is to increase the fast state determined by the posterior action.

The drawing shows the electrical structure of the device.

Variable frequency divider

The pulses entering bus 3 change the state of block 1 and the values of the levels at its outputs, which

the division factor contains p-times- you are decrypted using the switch25

thirty

a series counting block 1, the outputs of all bits of which are connected to the fixed contacts of each of the n multi-position switches 2-1 to 2-n, the additional fixed contacts of which are connected to the input bus 3 and to the clock input of the n-bit counting block 1, the movable contacts of each of the n multi-position switches 2-1–20 2-n are connected by Q with the corresponding inputs of the I 4 element, the output of which is connected to the reset input of the first trig I, hera 5, the clock input of which is connected to the output of the last discharge recount new block 1 and a clock input of the second trigger 6, the output of which through amplifier 7 is connected to its reset input and to the moving contacts of each of the n two-position switches 8-1 to 8-n, the fixed contacts of which are connected to the adjusting the inputs of the corresponding bits of the p-bit conversion unit 1; the output of the first trigger 5 is connected to the output bus 9.

The counting unit 1 can be performed on both binary elements (triggers) and multi-stable (or multi-position) elements. Multi-position switches 2-1 - 2-p in the case of use in the scaling unit 1 binary elements can be replaced with two-way.

The frequency divider with a variable division factor works as follows.

After the appearance at the output of the last bit of block 1 of a pulse (its front) trigger 5 switches to one state, on bus 9 the formation of output imtels 2-1 - 2-n and element 4 begins. Moment of coincidence of unit levels on moving contacts of switches 2 -1 - 2-n corresponds to the reset time of trigger 5. This completes the formation of the legs on the impulse on the tire 9. Thus, setting switches 8-1 to 8-p in certain states, adjusting the ratio, dividing the device, and setting switches 2-1 to 2-p in certain states, adjusting the duration of the output pulse.

40

45

50

Claims (1)

Invention Formula A variable divider frequency divider containing a n-bit scaling unit, the counting input of which is connected to the input bus, the output of each of the bits of which is connected to the corresponding scant non-moving contact of each of the multipoint switches j whose moving contacts are connected to the corresponding strokes element And, the output of which is connected to the reset input of the first trigger and the output bus, characterized in that, in order to improve speed, an amplifier is inserted into it and two-way switches It, the closing and opening contacts of each of which are connected to the installation inputs of the corresponding bit of the n-bit conversion unit, the switching - to the reset input of the second trigger and to the output of the amplifier, the input of which is connected to the output of the second trigger, the clock input which is connected to clock input of the first trigger, the output of which is connected to the output bus, and with the output of the last bit of the pulse. At the same time, it switches, yes, and an n-bit conversion unit, from to one state and flip-flop 6, the clock input of which is connected to the output signal of which, having passed through amplifier 7, sets flip-flop 6 to the initial zero state. additional fixed contact for each of the n multi-position switches. The impulse formed in this way, / passing through the switches 8-1 to 8-n to the installation inputs of the bits of block 1, will install this block in the sources of the specified switches. The pulses entering bus 3 change the state of block 1 and the values of the levels at its outputs, which decrypted using a toggle 2-1 - 2-p elements and element 4. The moment of coincidence of unit levels on the moving contacts of the switches 2-1 - 2-p corresponds to the resetting moment of the trigger 5. At the same time, the formation of the legs on the bus 9 pulse is completed. Thus, setting switches 8-1 to 8-p in certain states, adjusting the ratio, dividing the device, and setting switches 2-1 to 2-p in certain states, adjusting the duration of the output pulse. Invention Formula A variable divider frequency divider comprising a n-bit scaling unit, the counting input of which is connected to the input bus, the output of each of the bits of which is connected to the respective lean fixed contact of each of the n multi-position switches j whose moving contacts are connected by the corresponding strokes of the element And, the output of which is connected to the reset input of the first trigger and the output bus, characterized in that, in order to improve speed, an amplifier and p two-position switches are introduced into it It, the closing and opening contacts of each of which are connected to the installation inputs of the corresponding bit of the n-bit conversion unit, the switching - to the reset input of the second trigger and to the output of the amplifier, the input of which is connected to the output of the second trigger, the clock input which is connected to clock input of the first trigger, the output of which is connected to the output bus, and with the output of the last digit of the n-bit conversion unit, the clock input of which is connected to additional fixed contact of each of the n multi-position switches.