SU1297074A1 - Control device for fast discrete orthogonal transform processors - Google Patents

Abstract

The invention relates to computing and can be used to control a sample of 77 hw gz 10 f I P // information from storage devices in a wide class of processors designed for a wide range of signal processing tasks based on fast discrete orthogonal transformation algorithms. The purpose of the invention is to expand the functionality by calculating a truncated transform, a modified complex Hadamard transform, and a generalized discrete transform. The goal is achieved due to the fact that the device includes the element NOT 1, four elements AND 2, 3, 6 and 7, three elements IL 4.5 and 19, shift register of iterations 8, blocks of elements AND 9, 12 and 15 , subtracting counter 14, block of elements OR 13, counter of code 10, decoder 11, shaper of address 18, delay elements 16 and 17, and clock pulse generator. 1 il. with soy so about 4 gz

Description

The invention relates to computing and can be used to manage the sampling of information from storage devices in an extensive class of processors designed to solve a wide range of signal processing tasks based on fast discrete orthogonal transform (BDOP) algorithms.

The purpose of the invention is to extend the functionality by performing a truncated transform of the modified Hadamard cog shlex transform and a generalized discrete transform.

The device contains the element NOT 1, the elements AND 2 and 3, the elements OR 4 and 5, the elements AND 6 and 7, the shift register of iterations 8, the block of elements AND 9, the code counter (operations) 10, the decoder 11, the block of elements AND 12, the block elements OR 13, subtracting mean frequency 14, block of elements 15, delay elements 16 and 17, address generator (pair of operands) 18, element OR 19 clock generator 20, initial setup input 21, start processing input 22, mode input 23 operation, startup input 24, outputs 25 and 26 of the address of the real and imaginary parts of the operand, outputs 27-30 of the arithmetic code perazim.

The device works as follows.

When performing a direct BDOP, the positive potential (logic level 1) is applied to the input 22 of the device, which opens elements 2 and 7 and at the same time through element NOT 1 the same potential closes element 3 and element 6. the control unit input 21 and passed through the elements AND 2 and OR 4, the most senior. The register resolution of iterations 8 is set to I, all bits of the down counter 14 are also set to 1, and the control signal is output at the output of the element 15 eleme T 16 and the delay through the open AND gate 7 is supplied to the shift register 8. The input unit iterations of iterations significant bit of register B is shifted and zanosits through an OR gate 5 through the mounting entry into the low discharge iteration register 8, thereby preparing

(open) element AND block 9 to receive clock pulses TI. At input 24 of the control unit, GUI 20 is started and the clock pulses arrive at block 18 and to delay element 17. At block 18, with the arrival of each TI, the addresses of the operands of the real and imaginary parts are formed at the outputs 25 and 26, respectively. At the same time

With this, the zero state of the counter 10 in the decoder 11 of the code of the arithmetic operation at one of the outputs 27-30 produces an enabling potential for performing arithmetic operation in the arithmetic device.

Pervy TI, delayed by the time arithmetic operations,

from the output of the delay element 17 is fed to the subtractive counter i 4, its transfer to the state 111 ... 10, and also goes to the block of elements And 9 and further through the new open

the element AND to the counting input of the first digit of the counter 10, its transfer to the state 00 ... 01. This state of counter 10 is decrypted in decoder 11 and at its outputs 27-30

a new resolving potential appears. The second TI at the outputs 25 and 26 of block 18 forms the second pair of addresses of the first and second operands. After a delay in element 17 second

TI enters the counter 14 and transfers it to the state 111 ... 01. With the arrival of each successive TI in the counter 14, the next subtraction 1 is performed and this happens until

until the counter is reset to TI with the number N / 2-1. Next, after this TI, the counter 14 is set to the state 111 ... 1I and at the output of the element 15 produces a control potential, which, having passed the delay element 16 and the element 7, goes to the shift input of the register of iterations B and moves 1 from the first in the second digit of the register of iterations 8. The second TI also enters the block of elements And 9 and again through the open element And enters the counting input of the first digit of the counter 10, converting it to the state 00 ... 10. Here and

In all cases, then, except for the most recent iteration, counter 10 always counts to the counting path of the digit that corresponds to register bit 8 containing 1. On

the first iteration 1 in register 8 is in the first bit, so the counter 10 counts sequentially from the value 00.,. About up to 1 1. . . Г1, we are referring to N / 2 different states. At the second iteration I in register 8 is in the second bit, counter 10 counts as twos, accepting the states 00, .. О, 00 ... 10, 00 ... 100, 00 ... 110 and so on to the state 11 ... 10, and then the exact same counting cycle is repeated a second time. At the third iteration, counter 10 counts as quadruples, repeating the counting cycle 4 times, etc. With such an account organization, the output of the counter 10 appears all the necessary code addresses, which in the decoder 11 are deciphered into four groups of control potentials set at the output 27-30 of the device.

At the last nth iteration of the computations, the group of elements 8 and 9 is blocked by the absence of control potential from the register of iterations 8 and TI do not change the state of the counter of operation code 10, the remaining blocks work without changing. With the arrival of the last TI of the zero state And, from its output, the control signal, having passed the delay element 16, is fed through the element 7 to the shift input of the register of iterations 8. A unit shift signal from the high bit of the register of iterations 8 is entered by the element the ent OR 5 in the lower bit of the same register and at the same time the GTI is turned off along the element circuit 19. When performing reverse BDOP, a negative potential is applied to the control input 22 of the device, which closes the elements AND 2 and 7 and opens the elements through the NOT 1 element And 3 and 6. At the signal of the Initial Setup, fed to the input 21 of the control unit and passing through the elements AND 3 and OR 5, the low-order bit of the register of iterations 8 is set to 1, all bits of the counting counter 14 are also set to 1, while output element 15 and vyrabatyv a control signal which passes the delay element 16 and through the open AND gate 6 is supplied to the shift register 8. The input unit iterations of the least significant bit register is shifted iterations and

five

5 0 5

five

It is carried through the OR 4 element at the setup input into the high-order register of iterations 8. Otherwise, the entire operation cycle of the device is repeated with the only difference that the iteration register 8, the counter of operation code 10, start counting from left to right.

When truncated conversion at each subsequent iteration subtractive counter 14 operates with a reduction of two times. At the first iteration, there is no change in the operation mode of subtractive counter 14, and all units of the device operate as before. At the second iteration (1 in the second discharge of the register of iterations) when applying for input the truncated transformation of positive potential opens the first AND element from the block of elements AND 12 and through (n-2) the iteration the OR element from the block of elements OR 13 blocks the discharge p of the counter reading 14.

At the next iteration, two bits n and (n-1) of subtraction counter 14, and so on, are already blocked. And so, the subtracting counter 14 on the first iteration counts the full cycle, on the second, a half cycle and so on each subsequent iteration, the counting cycle of the subtractive counter 14 is halved.

Claims (1)

Invention Formula A control device for fast discrete orthogonal transform processors that contains an element NOT, four elements P, three elements OR, two delay elements, an address generator, a subtractor counter, an input shift register, the first And block, a code counter, a decoder, and a clock generator, the output of which is connected to the synchronization input of the address resolver and the input of the first delay element, the output of which is connected to the clock input of the subtractive counter and the first input of the first block of AND elements, you The one of which is connected to the counting input of the code counter, the output of which is connected to the input of the decoder, the output of the first AND element is connected to the first input of the first OR element, the output of which is connected to the installation input of the high bit of the iteration shift register, the output of which is the highest bit connected to the first inputs of the second and third elements OR, the outputs of which are connected respectively to the installation input of the lower bit of the shift register of iterations and the stop input of the clock generator, the start input which is the start input of the device, the output of the second delay element is connected to the first inputs of the second and third elements AND, the outputs of which are connected respectively to the control input of the right shift and the control input of the shift of the shift register of iterations, the output of the lower. which is connected to the second inputs of the first and third IGSh elements, the output of the element is NOT connected to the second input of the second element AND and the first input of the fourth element AND, the output of which is connected to the second input of the second element OR, the element stroke is not united with the second input of the third element AND, the first input of the first element AND is the input of the processing start of the device, the installation input of the detracting counter is combined with the second inputs of the first and fourth elements AND, and is the installation input of the device, and the information output is shifted. the register of iterations is connected to the second input Compiled by A. Baranov Editor T. Parfenova Tehred L. Serdyukova Proofreader I, Muska Order 783/53 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 0 5 0 five 0 the first block of And elements and the information input of the address formath, the first and second outputs of which are the outputs of the addresses of the real and imaginary parts of the operand of the device, respectively, characterized in that in order to expand the scope of application by using the device when performing a truncated transformation, the modified Hadamard complex transformation and a generalized discrete transform, the second and third blocks of AND elements and an OR element block, whose outputs are connected to the set The corresponding inputs of the corresponding rows of the subtracting counter, the information output of which is connected to the input of the second block of elements I, the output of which is connected to the input of the second delay element, the information output of the shift register of iterations is connected to the first input of the third block of elements And whose output is connected to the input of the block of elements OR, and the second entrance. of the third block of elements AND is the input of the setting of the mode of operation of the device, the output of the code of the arithmetic operation of which is the output of the decoder