SU1283955A1 - Generator of single pulses - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is increased reliability. The goal is achieved by introducing an element OR5 into the device. In addition, the device contains the first RS-flip-flop 1, the second 1K-flip-flop 2, the third RS-flip-flop 3, the AND 4 element Introducing the indicated element and the corresponding functional connections allows to increase reliability of the device. When exposed to an input signal of any duration, arbitrarily varying in time, and its repeated repetition, a single pulse with a duration of one cycle is output at the device output. 1 il.

Description

The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase the reliability of operation by receiving at the output of the device a pulse of one cycle duration regardless of the instant of occurrence and the duration of the input pulse and its repeated repetition.

The drawing shows an electrical functional scheme.

The shaper of single pulses contains the first RS-trigger 1, the second 1K-tr1-: yr ep 2; the third short-circuit trigger 3, element AND A, element 1 of SHI 5, the first input of which is connected to the input bus 6, the second input - with direct output

and t5

The level from the direct output will set the logic unit level at the input of element 5, and the level from the reverse output through element 4 will set the Zero state to trigger 1, which by output levels will allow the trigger 2 to switch to the zero state. On the trailing edge of the clock pulse, trigger 2 switches to the zero state and removes the signal of the logical unit from bus 8, when the input pulse from the bus 6 re-exerts on bus 8, the signal of the logical unit is absent, i.e. Trigger 1 will not switch because of the blocking of the input pulse on element 5 by a single level signal from the direct output of trigger 3, which will

the third RS flip-flop 3, output-20 is performed before the arrival of o6fVyfO

t5

The level from the direct output sets the level of the logical unit at the input of element 5, and the level from the inverse output through element 4 sets the trigger state 1 to the Zero state, which by output levels will allow the trigger 2 to switch to the zero state. On the trailing edge of the clock pulse, trigger 2 switches to the zero state and removes the signal of the logical unit from bus 8, and when the input pulse is repeated from bus 6 on bus 8, there is no signal of the logical unit, i.e. trigger 1 will not switch because of the blocking of the input pulse on element 5 by a single level signal from the direct output of trigger 3, which will be

20 produced before arrival o6fVy

From the 5th input of the first RS trngger 1, the direct output of which is connected to 1-B1; 7, direct output - with output bus 8, inverse output with 3 - input of the third RS-flip-flop 3, which is connected to the R-input of BTOpoi o IK-flip-flop 2, with the first input of the I 4 element and with the other set to the initial state 9.

The second input element And 4 is connected

with the inverse output of the third RS-trigger-35 move - with the K-input of the second 1K-flip-flop,

Hera 3; output - with the R input of the first RS flip-flop 1.

The shaper does as follows.

At the initial time, the pulse signal from bus 9 all triggers are set to zero, sse is set, and the second input of element 5 receives a zero potential When a signal is sent from bus 6 at the output of element 5, logic level O occurs, switching to TRGG - ger 15 which 5 switches, enables switching of trigger 2, at 50 on the trailing edge of the clock pulse trigger 2 sets to one state and generates a unit level signal on bus 8, and also switches trigger 3, whose C input is connected tobus clock pulses, direct output - with output bus, inverse output - with S-input of the third RS-flip-flop, element I, input bus, about tl and h-w sh, and so that, in order to increase reliability of operation, the zero state bus, the OR element, whose first input is connected to the input bus, are entered, the second input is with the direct output of the third RS flip-flop, the output is with the S input of the first RS flip-flop, and R is the input connected to the output of the element I, the first input of which is connected to the bus of the installation in the zero state and to the R inputs of the second. first, third IK- and RS-flip-flops, the second input with the inverse nkodom third RS TpHrrepa.

signal on the bus 9. Thus, when a signal of any duration, arbitrarily varying in time, is applied, and its repeated repetition, only one pulse B of one clock pulse is released at the output of the device.

thirty

Formula

the invention

A single pulse shaper containing the first RS-Trigger, the direct code of which is connected to the 1 input of the second 1K trigger, the inverse high input of which is connected to the bus of tat pulses, the direct output to the input bus, the inverse output to the S input of the third RS-flip-flop, element I, input bus, about tl and h aa w, and with the fact that, in order to increase reliability of operation, a zero state installation bus, an OR element, whose first input is connected to input bus, the second input - with direct output of the third RS-flip-flop, the output - with S-input of the first A second RS flip-flop, the R input of which is connected to the output of an I element, the first input of which is connected to the installation bus to the zero state and to the R inputs of the second, third IK and RS flip-flops, the second input with the third RS TpHrrepa.

Claims (1)

Single pulse shaper ^ containing the first RS-trigger, the direct output of which is connected to the 1-input of the second IK trigger, the inverse output - to the K-input of the second 1K-trigger, the C-input of which is connected to the clock bus, the direct output - output bus, inverse output - with the S-input of the third RS-flip-flop, element I, input bus, with the exception that in order to increase the reliability of operation, the zero-state bus is inserted into it, OR element, the first input of which is connected to the input bus, the second INPUT is direct! the output of the third RS-flip-flop, the output with the S-input of the first RS-flip-flop, the R input of which is connected to the output of the And element, the first input of which is connected to the zero bus and to the R-inputs of the second. th, third IK- and RS-flip-flops, the second input - with the inverse output of the third RS-flip-flop.