SU1228282A1 - Servo analog-to-digital converter - Google Patents

Abstract

The invention relates to a continuous-discrete conversion technique and is intended to build the following analog-to-digital converters of the decadal balancing with parallel control of the result of the coding of the increased speed. The invention allows to increase the speed and control the coding results by introducing into the next analog-to-digital converter containing a clock generator 12, the first decade of conversion, the first comparator, the HE elements 18-1 ... 18- (n-1) the first group, the third 9, the fourth 14, the additional 15 elements of AND, the counter 17, the n-1 decade of the transformation. With the beginning of a new conversion cycle and the appearance of a single signal at the output of element 9 I, the transmission of clock signals through element 14 to the input of counter 17, the capacity of which is equal to the maximum number of TajcTOB equilibration, is permitted. With the appearance of the zero signal of the end of the change, the counting of the clock signals by the counter 17 stops. When the counter 17 overflows and the identical signal of the element 9 AND on i is present (L C wujEZ 18- / | corner. /

Description

The output of element 15 And a single signal will be generated - a sign of conversion error, which is analyzed by the processor. With the systematic occurrence of any of the signals of the sign of a mismatch

The invention relates to the technique of continuous-discrete transformation and is intended to build the following analog-digital transducers of the decadal equilibration with parallel control of the result of the coding of high speed.

The purpose of the invention is to increase the speed and reliability of monitoring the coding results.

Fig. 1 is a block diagram of the following analog-digital device; figure 2 - block diagram of the logic unit.

The next analog-to-digital converter contains an input bus 1, a) decoding digital-to-analog converters 2-1 .., 2-n and reference sources; voltages 3-1 ... 3-p, first comparators 4-1 ... 4-P, second comparators 5-1., 5-p, logical blocks 6-i ... 6-n, first elements And 7-1 ... 7-P, second elements And 8-1 ... 8-P5 third element And 9, single-decade reversible counters 10-1 ... 10-p, triggers I1 -1 ... 11 -n, clock generator 12 ,, elements NOT 13-1., 3- (p-1) of the first group, fourth element And 14; the fifth element And 15, the sixth elements And 16-, 6-n, the counter 17j elements NOT 18-1., ..18-n of the second group, the start bus 19, the end 20 of the measurement end signal, the error signal bus 21. Logical blocks 6-1 ... 6-p are made on elements NOT 22, OR 23, delays 24.

The device works as follows.

In the initial state OUTPUT) 1e

; ignals of triggers li-l.,. tl-n and shemeny i 6 1.. . are equal to O. Tem; ama1 1 blocks the transmission of clock signals through the elements AND 7-1 .. -n and 8-I,. . 8-n per 1: yours

At the first output of logic blocks 6-1 ..., together with the error signal, measures can be taken to eliminate the failure. In the event of an accidental failure, an erroneous result is not read into the procesor. I zp f-ly, 2 ill.

0

five

0

five

0

0

five

inputs of one-decade reversible counters 10-1 .., 10-p. The contents of the counter 17 single-decade reversible counters 10 -... 0-n in the initial state are arbitrary.

The trigger signal (19 19) trigger I I -1 ... 1. -n set in single states, unlock elements And 16-1 ,, 16-p.

The A / D converters operate on the principle of balancing the measured value in a decade (decades of different stages) with varying voltage, forming 1) 1m single-decade, various-bit DACs 2-1 ... 2-P5 controlled by corresponding single-decade reversive counters 10-1. .10-p. The output voltage of the D / A converter for each successive lower bit of the sum {is. with the voltage of the DAC of previous high-order bits,

In the process of equalizing the output, each output of the DAC is set to a voltage equivalent to the values of the corresponding ten digit bits of the code of the measured value.

Two comparators 4-1 and 5-i are connected to the output of each of them, g de ... p. At the same time, the reference voltage of each comparator 5 is shifted relative to the voltage of the DAC by an amount of voltage equivalent to a unit of this bit of the DAC. The bias voltages are given by sources 3-1 ... 3-p.

Each comparator issues a single HH4HE; rft signal if the voltage at its reference input exceeds the value measured or is equal to it.

Each pair of comparators 4-1 and 5-1 controls the degree of inequality or inequality of the measured quantity to the set value of the balancing voltage at the level of the values of the corresponding code bits obtained in the previous conversion cycle and the same voltage

nigo DAC, but increased by an amount equal to

If the current sequential value of this and higher bits of the measured value code remains equal to that obtained in the previous countdown (conversion cycle), then comparator 4 (at the output of this DSL) keeps the zero value of its output signal unchanged, and the comparator 5 - a single value.

Comparator signals are analyzed in logical blocks 6-1 ... 6-P. If the signal of comparator 4-i is zero, and that of comparator 5-i is single, then at the first output of logic block 6-i the signal is zero (signal of the sign of zero error). This zero signal transmitted through the element AND 16-i blocks the transmission of the clock signals of the generator 12 through the elements AND 7-a and 8-1 to the counter circuits of the reversible counter 15-1 controlling the data converter DAC.

If the next actual value of the measured value exceeds the reference voltage set in the previous reference cycle at the input of the comparator 5-1 of this DAC 2-1, then this comparator 5-1 changes the output signal to zero. At the first output of the corresponding logic block 6-1, a single signal appears (the zero signal of the comparator 5-1 is inverted by the HE element 22), by which the elements AND 7-1 and 8-1 are prepared for transmitting the TOV-1X signals. With the indicated excess of the balanced voltage measured (undercompensation of the measured load) at the level of the code code by the signal of the corresponding comparator 5-1, inverted by a single element HE 22 of this analysis unit and transmitted from the second output of this logic unit 6-1 analysis of the associated element 7-1, it is allowed to transmit clock signals to the input of the direct count of this counter iO-i. For such signals, an increase in the voltage of the DAC 2-1 of this bit begins. With the appearance of a single signal of the comparator 5-1, which is included in the DAC circuit of this bit, the signal of the matching sign at the first output of logic block 6-1 becomes zero, the transmission of clock signals is blocked

The input to the input of the direct counter of a given DAC and the growth of the counterbalancing voltage by the steps of the given discharge stop.

If the current value of the measured voltage turned out to be less than the voltage of the DAC 2-1 of this bit set in the previous cycle, the output signals of the comparators 4-1 and 5-1 at the output of this DAC 2-1 will become unity. At the same time, the corresponding logic unit 6-1 at its first output also generates a single signal of the error sign. But due to overcompensation by a single signal of the corresponding comparator 4-1, transmitted via the third output of this logic block 6-1 to the AND 8-1 element connected to this output, it is allowed to transmit clock signals to the countdown input of the counter 10-1, which controls the data DAC. The output voltage of this DAC 2-1 begins to decrease as the clock signals arrive. When this voltage becomes less than the measured one, the corresponding comparator 4-1 changes the single signal to zero, the receipt of clock signals to the countdown input of this one decade reversing counter 10-1 is blocked, and the equilibration at the level of the code bit is completed.

With the completion of the balancing in the trades of this decade and the change in the signal of the error sign from the single to the outgoing element And 16-i switches to the third input the corresponding trigger 11-1, which is locked associated with, and the element 16-1. This eliminates the possibility of an oscillatory process in the case of noise and allows one to fix a fixed code value for its subsequent reading from single-decade reversible counters to the processor. The HE element 18-1 is designed to obtain the required logical value 0-1. The trigger switch signal on the third input.

If there is a mismatch within a decade of the previous high bit, a single signal of the sign of this error at the first output of the analysis logic block 6-1 in this decade is inverted by the corresponding element HE 13- (1-1), the zero signal of the element HE 13- (1-g) this blocks the possibility of balancing within the decade of the neighboring minor bit until the completion of the balancing within the decade of the preceding one. In addition, the signals of the HE elements I3- (i-I) prepare the corresponding elements I6-i for operation (block or unblock them) before the appearance of the trigger signal.

In the process of balancing, the mismatch sign may change in individual bits as the voltage of the DAC of the advancing high bits changes. In this case, the logical values of the output signals of the corresponding comparators 4-i and 5-1 are changed with the preservation of a single signal of the error sign at the first output of the corresponding logic block. With the indicated change in the signals of the comparators, a short-term parasitic pulse emission is possible at the output of the element OR 23 of the analysis block. To eliminate it and thereby eliminate its transmission to other elements of the device in logic blocks 6-1, a delay 24 element is used. The delay time of element 24 allows a few duration of the parasitic pulse so that its appearance does not change the set single signal on the first output of this logical block.

The signal of the low-order code discrepancy sign after the start / PW through the element 15 is transmitted to the variable 20. Changing the single value of this signal to zero is a sign of the end of the conversion cycle. By this signal, the code of the measured value from the outputs of all counters 10-1 ... 10-p. read into processor. After completion of the readout, the processor generates the next ADC trigger.

The next conversion cycle after the start signal arrives only if there is a mismatch signal, at least in the low-order analysis block.

With the beginning of a new conversion cycle and the appearance of a single signal at the output of element 9, the transmission of clock signals through the element 14 to the input of counter 17 is allowed, the capacity of which is equal to the maximum possible number of ADC equilibration cycles increased by one. With the advent of the zero signal of the end of the measurement, the counting of the clock signals of the counters 7 is stopped and when the ADC is next started, this counter is reset to the zero state.

When counter I7 overflows and there is a single signal from element 9 at the output of element 15, a single signal is generated (a sign of conversion error), which is analyzed by the processor. With the systematic occurrence of any of the signals of the error sign (the first output of blocks 6-1 ... 6-P together with the error signal), measures can be taken to eliminate the failure. In the event of a random failure, an erroneous result is not read into the processor.

Claims (2)

1. The next analog-to-digital converter containing a clock generator, the first decade of the conversion performed on the first and second elements AND, a trigger, a one-decade reversible counter and a digital-analog converter, the first inputs of which are connected to the outputs of a one-decade reversible counter, and the output is connected to the first input of the first comparator, the second input of which is an input bus, the output of the second element I is connected to the first input of a one-decade reversible counter, characterized in that, in order to increase actions and reliability of the conversion results, n-1 elements of the first group are NOT entered into it, the third, fourth and fifth elements are AND, a counter, n-1 decades of transformations performed similarly to the first, and the sixth AND element is entered into each 1st decade of transformation , NOT element of the second group, second comparator, voltage source, logic unit, the first input of which is connected to the output of the first comparator, the second input - with the output of the second comparator, the first input of which is an input bus, the second input through the source of supports th voltage connected to the output single-decade digital-analog converter, the second input of which, besides the single-decade digital-analog converter of the fifth decade of conversion, where n is the senior decade of the conversion, is connected to the output of the diffraction-analog converter (1 + 1) -th decade of conversion, the first output of the logic block is connected the first input of the sixth element I, the second input of which, besides the element of the I-th decade of transformation, is connected via the element of the first group to the first output of the logical block (1 + 1) -th decade of transformation, the third input of the The first input of the trigger is connected to its inverse output, the second trigger inputs of all decades of conversion are interconnected with the first input of the counter and are the Start bus, the third trigger input of each conversion decade is connected to the output of the NOT element of the second group, the input of which is combined with the first inputs of the first and second elements And and is connected to the output of the sixth element And, and the output of the first element And is connected to the second input of a single-decade reversible counter, the second input is connected to the second output of the log eskogo unit, the third output is connected to the second input of the second AND gate, the third input of which is combined with a third input of the first elementary P r. Compiled by A. Kuznetsov Editor T. Miteiko Tehred I. Veres Corrector. Order 2297/58 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4 mA of the i-th-decade conversion and the third inputs of the first and second elements AND (i + l) -x decades of conversion, the first input of the fourth element I and connected to the output of the clock generator, the second input of the fourth element I combined with the first input of the fifth element And is connected to the output of the third element And is the signal bus. The end of the measurement, the output of the fourth element And is connected to the second input of the counter, the output of which is connected to the second input of the counter, the output of which is connected to the second input of the fifth element And, the output of which is second error signal, the first output of the third AND gate .. connected to the inverted output of the flip-flop of the first decade conversion, the second input - to the first output of the first logical block converting decades. 2. The device according to claim 1, TL is - that the logic unit is executed on the delay elements NOT, OR, the first input — of which is the first input and the third output of the logic unit — the second input is connected to the output of the element NOT and is The second output of the logic block, the input of the element is NOT the second input of the logic block, the output of which is the output of the delay element whose input is connected to the output of the OR element.