SU1198505A2 - Device for preprocessing information - Google Patents

Abstract

DEVICE FOR PRELIMINARY PROCESSING OF INFORMATION on aut.St. No. 1062684, about the ti and-: in order to expand the functionality of the device by creating states of discrete signals of the information flow, the first and second registers, the comparison unit, the first input of which is connected to the first registers, are entered into it. the information output of the memory block, the second input of the comparison block is connected to the information output of the time counter, the output of the second register is connected to the second input of the first register, the third input of which is connected to the output of the comparison block, course of the first register is connected to the third infor (A mation entry switch.

Description

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The invention relates to computing, can be used in debugging and testing process control systems, as well as in various types of simulators and simulators working in conjunction with a computer, and is an improvement of the known device according to author. No. 1062684.

The purpose of the invention is to expand the functional capabilities of the device by generating the states of the Discrete signals of the information flow being processed at a time determined by the request.

The drawing shows fu1 {K11, and the circuit diagram of the device.

The device contains a data input block 1, a buffer memory block 2, a memory block 3, a time counter 4, an arithmetic unit 5, an encoder 6, a delay element 7, a switch 8, a comparison block 9, a predetermined state register 10 and a current state register 11 neither, control input 12 of the device, information output 13, control E1; i output 14, information input 15 of the device.

The principle of operation of the device is based on computing at the time of arrival, requests from a computer, or the value of the reproduced analog signal at the interpolation segment specified by the codes of its beginning, end, and duration, or the formation of the state of the reproduced discrete signal by comparing the specified and current times.

The number of conversion channels depends only on the amount of memory used, as well as the size of the encoder and switch, which determines the addressing capabilities.

At each moment in time, the device stores information of two frames - the current and the next. Each frame contains coefficients, determining the value of analog signals at interpolation nodes, or the time and the sign of the change of discrete signals and the value of the interpolation interval C; common for all conversion channels, as well as an array of delay values for the output of information dp of each channel, selected so that

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the receipt of computer information in response to a request corresponded to the time it passed through the system of communication devices with the object.

5 After the interpolation interval of the current frame expires, the time of the subsequent frame begins, and information for the new frame is entered into the device. This update

10 information occurs regardless of the presence or absence of requests from the computer.

The device works as follows.

15 In the initial state, in block 3 of memory, the coefficients k and k are stored for all conversion channels and the corresponding delay values. The value of the interpolation interval 6, is entered into the arithmetic unit 5 and the counter 4 times. The information for the second frame, i.e. the coefficients K "of all the conversion channels, the corresponding values of the delays and the interval value. interpolation tJg of the second frame is in block 2 of the buffer memory. Upon receipt of a command input 12 command request from a computer

30, the encoder 6 generates a code arriving at the input of memory block 3, like the address of the K-factors and K values of an analog signal or a group of values of discrete signals,

22 and to the control input of the switch 8 as the input address of the information in the computer. The values of the coefficients selected by addresses, formed by the encoder 6, from the output of memory block 3

40 are fed to the arithmetic unit 5, to the registers 10 and 11 and the unit 9 of the signal comparison. The arithmetic unit 5 according to the obtained values of the coefficients K, and K the value of with and

The 45 value of the current time on the interpolation interval t, received from the counter 4 time, determines the value of the analog signal at the time of the survey in the form of a code

50 -1 (K - K, h,) -t / C; J which from the output of block 5 is fed to the first information input of the switch 8.

From the second output of the block 3 of the memory 55 to the input of the delay element 7 implemented on the basis of the counter, a code is received that determines the delay time of the analog and discrete

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signals. From the output of the delay element 7, the connection resolution signal goes to the first information input of the switch 8, the control input of which has a code defining the input address of the information in the computer.

When a group of coefficients K-, K | that determine the time and signs of the state of discrete signals are received over N channels from block 3, they are distributed as follows: signs of the state contained in The register 10 of the specified state records the signs of the state contained in K, and the specified times of state change (T, -, where j 1, N) go to the corresponding comparison circuit of the comparison block 9, to the second input of which (all the comparison circuits ) comes the value of the current time t from the counter 4 times. Registers 10 and 11 each contain N bits, each of which determines the state of one discrete signal, and the compare block 9 contains N independent comparison circuits in accordance with the level of the reproduced discrete signals in the group. In the case of Tj-t in any of the discrete channels, the corresponding comparison circuit of block 9 compares the recording information enable signal from register 10 to the corresponding register bit 11. Thus, information defining the state of the group of discrete signals at the moment survey. G output register 11 of the current state of the information on the third 98505

The information input is fed to the switch 8, the control input of which has the code specified by the encoder 6. Thus, at the moment the signal arrives at the first information input of the switch from the delay element 7, the information determining the value of the analog signal or the discrete state

10 signals at the time of the survey, can be read from the information output 13 of the switch 8.

Since the frame information is stored in the device memory unchanged

15 until the end of processing the interpolation interval t i. before filling counter 4, the request from the computer can be repeated on an arbitrary or former channel and at output 13

20 of switch 8, new values of analog or discrete signals will be obtained at the moment of polling.

Upon completion of the filling of the counter 4, a request for information for the next frame is formed at its control output 14. At this request, input 15 of block 1 of input from an external source of information is received

The 30 codes of the next frame of information are recorded in block 2 of the buffer memory.

Here, the coefficients determining the values of the analog signals,

The time and indications of the state of discrete signals for the next frame are copied from block 2 of the buffer memory to block 3 of memory, and the value of the interpolation interval is written into the arithmetic unit 5 and counter 4 of time. In the future, the device operates in accordance with the specified algorithm.

Claims (1)

DEVICE FOR PRELIMINARY INFORMATION PROCESSING on ed. No. 1062684, characterized in that, in order to expand the functionality of the device by forming states of discrete signals of the information stream, the first and second registers are introduced into it, a comparison unit, the first input of which is connected to the first inputs of the registers and the first information output of the memory block, the second Input the comparison unit is connected to the information output of the time counter, the output of the second register is connected to the second input of the first register, the third input of which is connected to the output of the comparison unit, the output is a third register connected to the data input of the switch.