SU1190507A1 - Pulse-width modulator for servo electric drive - Google Patents

Abstract

A WIDE-PULSE MODULATOR FOR A FOLLOWING ELECTRIC DRIVE containing the first and second comparators, the first inputs of which are connected to the outputs of the bias voltage source, respectively, and the second with the input source output, connected in series with a triangular-shaped voltage generator and inverting amplifier, as well as a matching element and an inverter, characterized in that, in order to increase the efficiency of the modulator by eliminating the "chatter in the small signal area without reducing accuracy, an element is introduced into it t OR-NOT, a trigger, an OR element and a dual capacitor, the first input of which is connected to the output of a triangular voltage generator, the second input to the output of the input source, the third input to the output of the inverting amplifier, and the output to the first output bus of the device , the output of the first comparator is connected to the first input of the OR-NOT element and the S-input of the trigger, the output of which is connected to the first input of the matching element, the second input of which is connected to the output of the OR-NOT element, and the output to the first input of the OR element, sec i th input is connected to the R-input of the flip-flop, a second input of OR-NO element and the output (A second comparator, and an output - a second output bus of the device and through an inverter to the third output device bus.

Description

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The invention relates to a pulse technique and can be used in following electric drives with static pulse-width converters.

The purpose of the invention is to increase the efficiency of the pulse-width modulator by eliminating, "chatter in the small signal area without reducing accuracy by forming a static relay characteristic with a leading loop to form the sign of the output signal.

Figure 1 shows the structural scheme of the pulse-width modulator; Fig. 2 is a timing diagram of the formation of an output quantity proportional to the module of the input signal; FIG. 3 is a timing diagram of the formation of logical signals at the sign outputs of the modulator.

Pulse-core modulator contains input source 1, comparators 2 and 3, dual comparator 4, triangular voltage generator 5, inverting amplifier b, bias voltage sources 7 and 8, OR-NOT element 9, trigger 10, element 11 matches, the element OR 12, the inverter 13, the output bus, the input source 1 is connected to the first inputs of the comparators 2 and 3, the second inputs of which are connected respectively to the source 7 of the positive bias voltage and the source 8 of the negative bias voltage, output comparator 2 is connected to the first input of the Element OR-NOT 9 and S-BXO of the trigger 10, the output of which is connected to the first input of the element 11 matches, the second input of which is connected to the output of the element OR-NOT 9, and the output to the first input of the element OR 12, The second input of which is connected to the R input of the trigger 10, the second input of the element OR NOT 9 and the output of the comparator 3, and the output to the output bus 15 and through the inverter 13 to the output thickness 16, the output of the dual comparator connected to the output bus 14, and its inputs, respectively, with the output of the generator 5 triangular on the voltage of the output source 1 of the input signal and the output of the inverting amplifier 6, the input of which is connected to the output of the generator 5 of the triangular voltage.

The dual comparator 4 can be made on the basis of two indentical comparators united on the output by the OR element, for example, on the basis of the 521CA1 chip.

The modulator operates as follows.

The input signal UBX from source 1 is compared on a dual comparator 4 with antiphase triangular reference voltages Uoi and Uo2 from generator 5 and inverting amplifier 6, as shown in the time diagram of voltages 2.

In this way, on the output device chin 14, the formation of

pulses, the fill factor of which is proportional to the modulus of the input signal.

The formation of single logical signals on the output shafts 15 and 16 of the device, equivalent to the sign of the input signal UBX, is carried out according to the law of the relay characteristic with a leading loop (Fig. 3).

The input signal UBI from source 1 is compared at comparator 2 and 3 with a positive + U | and negative -Ui bias voltages from sources of respectively 7 and 8.

With UBX + Ui, a logical "1" signal is generated at the output of the comparator 2, and a logical signal "O" is output at the output of the comparator 3. At the same time, the logical element "O appears at the output of the element OR NOT 9", and the logical "1 appears at the output of the trigger 10, so the output of the element 11 matches will be a logical" About, respectively, at the output sign buses 15 and 16, the device signals the logical " Oh and “1.

With UBic -4-Ui, at a time ti, the output of the comparator 2 is a logical signal "O at the output of element 9 OR-NOT 9 appears" 1, and the trigger 10 of its logical state "1 does not change at the output, therefore, at the output of the coincidence element 11, a change of the logical state to a logical "1" occurs, and then at the output wakes 15 and 16 of the device, the logical signals are changed to "I and" O ".

At 1, the state is preserved, and the time point at the output of the comparator 3 appears as a "1" signal, and therefore at the output slots 15 and 16 of the device also

5 remain the same signals, respectively, "1 and" O. In this case, the state of the trigger 10 is changed to a logical "O, the logical element" O appears at the output of the matching element 11. With UBS-Ui, the state on the output buses 15 and 16 of the device is not

0 varies.

At time point 1z, when Uex-Ui at the output of the comparator 3 a logical "O" signal appears, at the output of the element ORIS NOT 9 the state changes to "1, but the state of the logical" O trigger 10 remains, therefore at the output of the element 11 matches, the state "O is also preserved; consequently, there is a change of states on the output buses 15 and 16 of the device -

0 pov nggs signals, respectively, "O and" 1.

With a further increase in the input signal UBX, the state on the output buses 15 and 16 of the device remains, but at time t4 the output of the comparator 2 appears "1, the state of the trigger 10 changes to the opposite, and thus the circuit returns to its original state .

Thus, eliminating bounce in the small signal area without reducing accuracy is achieved in that the change in the sign of the output signal of the pulse-width modulator is carried out according to the relay characteristic with a leading loop, which is formed with the help of the newly introduced OR-NOT, OR trigger elements.

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Claims (1)

WIDTH-PULSE MODULATOR FOR THE NEXT ELECTRIC DRIVE, containing the first and second comparators, the first inputs of which are connected to the outputs of the bias voltage sources, respectively, and the second to the output of the input signal, connected in series to a triangular voltage generator and an inverting amplifier, as well as a coincidence element and an inverter , characterized in that, in order to increase the efficiency of the modulator by eliminating the "bounce" in the region of a small signal without compromising accuracy, an IL element is introduced into it NAND, a trigger, an OR element, and a dual comparator, the first input of which is connected to the output of a triangular voltage generator, the second input is connected to the output of the input signal source, the third input is connected to the output of the inverting amplifier, and the output is connected to the first output bus of the device, the output of the first comparator is connected to the first input of the OR-NOT element and the S-input of the trigger, the output of which is connected to the first input of the coincidence element, the second input of which is connected to the output of the OR-NOT element, and the output to the first input of the OR element, the second input It is connected to R-input of the flip-flop, a second input of OR-NO element and the output of the second comparator, and an output - a second output bus of the device and through an inverter to the third output line of the device.