SU1175020A1 - Controlled delay device - Google Patents

Abstract

A DEVICE OF A REGULATED DELAY, containing a counter, the counting input of which is connected to the input reference signal bus, a comparison unit, the first inputs of which are connected to the outputs of the counter, a buffer register, the information input of the countergroup is connected to the information transfer bus, and the clock input is connected to the output of the first NAND element, the first input of which is connected to the clock signal bus, and its second input to the signal bus request and to the input of the inverter, the output of the comparator unit is connected to the information input of the first D-flip-flop, clock the input of which is connected to the counting input of the counter and the clock inputs of the second and third B-flip-flops and the inverse output of the third D-flip-flop is connected to the first input of the second AND-NES element, so as to increase the allowable rate of change of the delay output signal while simultaneously reducing the hardware volume, a coincidence element and a fourth D-flip-flop are inserted into the device, the installation input of which is connected to the inverter output and the installation input of the second D-flip-flop, the inverse output of the fourth D-flip-flop connected to its information input, and the direct output is connected to the input of the setup of the first D-flip-flop, the inverse output of which is connected to (L output bus of the device, and to the first input of the coincidence element, the output of which is connected to the clock input of the fourth D-flip-flop and the second input of the coincidence element is connected to the output of the second NAND element, the second input of which is connected to the direct output of the second D-flip-flop and to the installation input of the third D-flip-flop, and the information inputs of the second and third D-flip-flop; edi Itza logical signal, and outputs bufer1nogo register connected to the second inputs of the comparing unit.

Description

one

The invention relates to radio engineering and can be used as an actuator for automatic control systems in frequency, phase, or time delay.

The purpose of the invention is to increase the permissible rate of change in the delay of the output signal while reducing the instrumental volume.

FIG. 1 shows a functional diagram of the proposed deviceJ in FIG. 2 - diagrams of the device.

An adjustable delay device (Fig. 1) contains a counter 1, the counting input of which is connected to the reference signal bus, a comparison unit 2, the first inputs of which are connected to the outputs of counter 1, a buffer register 3, whose information input is connected to the information transfer bus, and a clock input connected to the output of the first e-element AND-NOT 4, the first input of which is connected to the bus clock signal, and its second input is connected to the signal bus request and the input of the inverter 5, the output of which is connected to the installation inputs of triggers 6 and 7, the inverse output of the D-trigger 6 is connected to its information input, and the direct output is connected to the installation input of the D-flip-flop 8, the inverse output of which is connected to the output signal bus and to the first input of the coincidence element 9 whose output is connected to the clock input of the D-flip-flop 6, and the second input element 9 coincidence is connected to the output of the element AND-NOT 10, the first input of the second is connected to the inverse of the D-flip-flop 11, and the second input of the element IS-NE 10 is connected to the output of the flip-flop 7 and the installation input of the flip-flop 11 7, 8 and 11 are connected to the counting input of the account snip 1, plaque-eye output 2 is connected to the comparator input informatsionnpu D-flip-flop 8 and the data inputs of D-flip-flops 7 and 11 are connected to a source of logic-one signal.

The device works as follows.

The counting input of the counter 1 receives pulses with a repetition rate

750202

f. When this occurs, a periodic change of the code recorded in the counter 1 with the period k / f (Fig.2a :). The current code At from the outputs of bits 5 of counter 1 is fed to the first inputs of comparison unit 2, the second inputs of which receive code Bj (Fig. 24) from the outputs of buffer register 3. When changing information in the buffer

o register 3 at the output of the NANDA element asynchronously with a sequence of pulses f (, a Request signal is received. (Fig. 2o), which ensures that the char 5 of the synchro pulses are passed to the buffer input to the clock input of the buffer5 register the register is sequentially entered by the code BJ controlling the delay of the output pulse arriving from

Q bus Information on the information input of the buffer register 3. In addition, the signal request through the inverter 5 is fed to the installation inputs of D-flip-flops 6 and 7 and translates them

5 direct outputs in the state of logical O.

Pulses with a repetition rate j (fo / k) are generated at the output of the comparator unit 2, synchronously with the moments of the input codes coincidence. In addition to the useful pulses, there will be parasitic pulses at the output, which are caused by the influence of the final delays and the response time of the real elements of the counter 1 and comparator unit 2. For filtering parasitic pulses, the signal from the output of comparator unit 2 is fed to the information input of the D-flip-flop 8. At the same time, the installation signal (Fig. 2e) from the direct output D-tr acts at its installation input. ggera 6. It blocks the D-flip-flop 8, while its inverse output signal is set to logic 1 (fig.2.3). piped to the first coincidence vh.od member 9 and on the output device.

0 from the output of the D-flip-flop 7, a logical O signal (Fig. 2 and) is fed to the second input of the NAND element 10 and to the input of the D-flip-flop 11, at the inverse output of which a logical 1 signal is generated (Fig. 2e).

When the recording of information into the buffer register 3 is completed, the first pulse 3 of the ff sequence, received after the signal is removed, the Request (Fig. 2) translates the direct output of the D flip-flop 7 to the logical 1 state (Fig. 2). The next pulse, according to succession fff, transfers the inverse output of D-flip-flop 11 to the state of logical O (Fig. 2). At the output of the NAND-NE element 10, a single pulse is generated that passes through the coincidence element 9 and arrives at the clock output of the D-trigger 6 By the falling edge of the pulse, the direct output of the indicated D-flip-flop is transferred to the straight-forward 1 state. At the same time, the prohibition on the output of the D-flip-flop 8 signal 204 (Fig. 25) from the input signal from the comparator 2 is removed. The pulse of the output signal (Fig. 2K) through the coincidence element 9 is fed to the counting input of D-flip-flop 6 and the trailing edge transfers its direct output to the logical state O. This logical O is fed to the setup input of D-flip-flop 8 (Fig. 2e) and re-blocking its operation. Simultaneously with the beginning of a new pulse on the bus, the request for direct and inverse outputs of D-flip-flops 7 and 11 are transferred respectively to the state of logical O (Fig. 21) and logical 1 (Fig. 2d), the operation cycle of the proposed device repeats.

Claims (1)

A CONTROLLED DELAY DEVICE containing a counter, the counting input of which is connected to the input reference signal bus, a comparison unit, the first inputs of which are connected to the counter outputs, a buffer register, the information input of which is connected to the information transfer bus, and the clock input is connected to the output of the first AND element “NOT, the first input of which is connected to the Sync signal bus”, and its second input to the Request signal bus and to the input of the inverter, and the output of the comparison unit is connected to the information input of the first D-trigger, the clock input to which is connected to the counter input of the counter and to the clock inputs of the second and third D-flip-flops, and the inverse output of the third D-flip-flop is connected to the first input of the second AND-NOT element, which differs in that, in order to increase the permissible rate of change in the output delay signal while reducing the hardware volume, a coincidence element and a fourth D-trigger are inserted into the device, the installation input of which is connected to the inverter output and the installation input of the second D-trigger, the inverse output of the fourth D-trigger is connected to it and formation input, and the direct output is connected to the installation input of the first D-trigger, the inverse output of which is connected to the output bus of the device, and to the first · ”input of the coincidence element, the output of which is connected to the clock input of the fourth D-trigger, and the second input of the coincidence element connected to the output of the second AND-NOT element, the second input of which is connected to the direct output of the second D-trigger and the installation input of the third D-trigger, and the information inputs of the second and third D-trigger: the ditch is connected to the signal source of the logical unit cts, and the outputs of the buffer register are connected to the second [inputs of the comparison unit. 1175020 2