SU1172053A1 - Cycle synchronization device - Google Patents

Abstract

1. SYNCHRONIZATION DEVICE BY CYCLES, containing serially connected code analyzer and first element I, serially connected first frequency divider, first prohibition element and first counter, serially connected second element And, second, divisor partby, second prohibition element and second counter, serially connected clock generator and distributor, with the clock generator output connected to the clock inputs of the first and second frequency dividers, and the information input is recuperators code is input apparatus of Whitlock ich. And in order to reduce the time of entry into synchronism, the service dressing analyzer, the first and second triggers, the first and second additional AND elements and the OR element are entered into it, while the output of the code analyzer is connected to the first control input of the analyzer the service parcel, to the combined first inputs of the second element And and the first and second additional elements And, and to the combined prohibitory inputs of the first and second elements of the prohibition, the clock and second control inputs of the analyzer connected to the outputs of the clock pulse generator and distributor, and the information input of the service analyzer service subkeys to the information input of the code analyzer, the output analyzer service aisle connected to the combined installation inputs of the distributor, code analyzer and the first and second frequency dividers, the output of the first frequency divider -, connected to the second input of the first additional element I, the output of which through the first counter and the & amp & ment OR is connected to the permitting (L C input of the distributor, the output of the second frequency divider is connected to the second input of the second additional AND element, the output of which through the second counter is connected to another input of the OR element, the outputs of the first and second prohibition elements are connected respectively to the inputs Set 1 of the first and second triggers, inputs Installation About which are connected respectively to the auxiliary outputs of the first and second frequency dividers, the forward outputs of the first and second triggers are connected respectively It is essential to the second inputs of the first and second elements I, the inverse output of the first trigger is connected to the third input of the second element I, and the output of the first element I is connected to the enable input of the first frequency divider. 2. The device according to claim 1, characterized in that the analyzer is package contains after

Description

the first key block, the first shift register, the second key block, the second shift register and the decoder, the first AND element, the IL element and the counter, the first NOT element and the second AND element, as well as the third shift register, the first and the second elements of the prohibition, the second and third elements are NOT and the third element is AND, and the clock input of the third shift register is connected to the combined first inputs of the first element AND and the first element of the ban and the second input of the second element AND, OUT The first M bits of the third shift register are connected respectively to the M information inputs of the first key block, the output (M + 1) of the third shift register is connected to the input of the second element NOT and to the second input of the first element I, the output (2М + 1) -th bit of the third shift register is connected to the input of the first element NOT and to the third input of the first element AND, the input of the third element

NOT and the fourth input of the first element AND are connected to the output of the first discharge of the third shift register, the outputs of the second and third elements are NOT connected respectively to the second and third inputs of the second AND element, the output of which is connected to another input of the OR element, the second input and the output of the first prohibition element connected respectively to the output of the IZH element and the Reset input, the output of which is connected to the control input of the first key block, the control inputs of the nepiBoro shift register and the second key block are connected Respectively to the outputs of the third element And the second prohibition element, the combined first inputs and the combined second inputs of the third element And the second prohibition element are respectively the first and second control inputs of the analyzer, the clock and information inputs of the third shift register are respectively the clock and the information inputs of the analyzer and the outputs of the decoder are the outputs of the analyzer.

The invention relates to telecommunications and can be used in data transmission systems to provide cycle synchronization.

The purpose of the invention is to reduce. time of entry into synchronism.

FIG. Figure 1 shows the electrical block diagram of a cycle synchronization device; in fig. 2 - structural electrical circuit. Service posyp-7 analyzer of kn. .

A device to synchronize on. cycles contains analyzer 1 service parcel, generator of 2. tact pulses, distributor 3, analyzer 4 codes, first element 5, second element b, first trigger 7, second trigger 8., first frequency divider 9, second divider 10 hrs. tots, the first element 11 of the ban, the second element 12 of the ban, the first, an additional element And 13, the second

an additional element And 14, the first counter 15, the second counter 16 and the element OR 17.

The service parcel analyzer contains the third shift register 18, the first prohibition element 19, the first, second and third prohibition elements 20-22, the first and second AND 23 and 24 elements, the OR 25 element, the counter 26, the third And 27 element, the second prohibition element 28 the first key block 29, the first shift register 30, the second key block 31, the second shift register 32, the decoder 33,

The cycle synchronization device operates as follows.

In accordance with the previously established mode of operation, the analyzer 1 (Fig. 1) outputs a control signal to the distributor 3, the analyzer 4, the first 9 and the second divider 10, which, according to this signal, are set to work with the corresponding block code. The information received at the information input of the synchronization device is entered into the analyzer 4 in bits, the output of which at a clock frequency is the signals 1 when it matches and O when the n-bit sequence of binary symbols does not conform to the code construction law. If at the moment of arrival of the next pulse corresponding to the output of the analyzer 4 there is no synchronism in the operation of the device for synchronization of the cells, the first and second triggers 7 and 8 are in a state into which they will be transferred by a signal from the outputs of the first and second elements 11 and 12 prohibitions when the previous pulse matches the pulse at the output of the first and second dividers 9 and 10, then the next pulse matches the output of the analyzer 4. if there is an enable signal i from the first output of the first igger 7 passes through the first element AND 5 and starts the first divider 9, which from this moment begins to divide the clock frequency | d1 from generator 2 one time. After one clock after launch, the additional output of the first divider 9 appears which enters the installation About the first trigger 7 and sets it to the zero state, in this case the enabling signal on the second input of the first element 5 is removed and the restart of the first divider is prevented; 9 at the time of the analysis of the periodicity of the appearance of pulses according to the initial phase established in the first divider 9. Simultaneously, the inverting output of the first trigger 7 to the third input of the second element And 6 is given an enable signal to pass through this element the next matching pulse, which can occur at subsequent beats of the input sequence. If the pulse that triggered the first divider 9 corresponds to the true phase, then a pulse appears at the output of the first divider 9, which coincides in time with the matching pulse at the output of analyzer A and passes through the first additional element I 13 to the counter 15. Through the specified number of cycles, if the signal corresponding to the output of analyzer 4 appears regularly in each cycle, counter 15 overflows, and the pulse from its output passes through the OR element 17, starts distributor 3. If in any cycle the match signal at analyzer output 4 is absent, then the pulse from the output of the first divider 9 passes through the first prohibition element 11, resets to its original state, the counter 15 and sets the first trigger 7 to the first state, preparing the cycle synchronization device for a new analysis cycle . If, during one cycle, a second impulse appears at the output of analyzer 4, then it, if there is an enable signal from the inverse output of the first trig repa 7 and an enable signal from the direct output of the second trigger 8, passes through the second element. . And 6 and starts the second divider 10. In the future, the work of the second divider 10, the second element 12 of the ban, the second additional element And 14, the second trigger 8 and the second counter 16 is similar to the work of the first channel of the synchronization device on cycles, containing the first element And 5, the first divider 9, the first prohibition element 11, the first additional element And 13, the first trigger 7 and the first counter 15. In parallel, the analyzer 1 at the end of each true cycle when receiving a signal of inconsistency of the received code combination to the code construction law 4 of the analyzer checks the received combination on its belonging to a service package. If the resulting combination is assigned to a service one, then, based on the information J contained in it, a corresponding control signal is generated to the distributor 3, the analyzer 4 and the first and second dividers 9 and 10, preparing these elements for working with the new code. In this case, in the distributor 3, the first and second dividers 9 and 10, the coefficient changes. division. In the future, the cycle synchronization device works in a similar way. The next cycle pulse at the output of the distributor 3 appears exactly after the duration of the new cycle. This will ensure a synchronous transition to the new mode of operation without additional cerida for synchronization.

For uniqueness and independence of the algorithm of operation of the analyzer 1, the law of building service / dressing should be the same for all possible modes of operation of the data transfer system. The service box can be formed as follows: on the site of the information bits of the system code, a multiple repetition of the t-bit combination corresponding to the new mode of operation is placed, and the control symbols received from the information part of the code are replaced with inverted ones. Thus, a forbidden code combination is formed with repeated repetition of the m-bit control combination. The criterion for receiving such a service parcel may be, for example, three-fold repetition of the m-bit combination for the length of the information part of the parcel and its inconsistency with the code construction law.

Such a construction of the service dressing, together with the stated acceptance criterion, ensures a high probability of its correct reception, as well as a reliable allocation of the service parcel even if the receiving and transmitting parties diverged in the modes of operation. To restore the mode of operation, it suffices to repeat the service message and transmit after it the sequence of allowed code combinations necessary for the implementation of the full cycle of entering sync.

The information supplied to the information input of the analyzer 1 is bitwise entered into the third register 18 (Fig. 2) with a capacity of (2 t + 1) bit. On each clock cycle, the content of the 1st, (t +1) and (2 t + l) -io bits If the contents of these bits coincide and equal to 1, then the output of the first element I .23 is a single pulse, which passed through the element OR 25, enters the input of the counter 26. If the contents of these bits are 0, then the signals from the outputs These bits are inverted on the first, second, and third elements, NOT 20-22, arrive at the second element, AND 24, and from its output as a single pulse, pass through the element OR 25, arrive at. the input of the counter is 26. If the content of these bits does not match, then the pulse at the output of the element OR 25 does not appear and thus the passage through the first element 19 of the prohibition is permitted. clock pulse to input Reset counter 26, which is reset. When a sequence of information symbols appears in a sequence of three repetitions of any m-bit pattern, a sequence of m pulses is formed at the output of the OR 25 element, the counter 26 overflows and the pulse from its output allows writing the contents of the first m bits of the third register 18 through the first block 29 of keys in the first register 30, where this information is stored until the end of the cycle. At the end of the cycle, if the analyzer 4 (Fig. 1) receives a signal corresponding to the code combination to the code building law, then an output is generated at the output of the third element 27 (Fig. 2) that erases the information stored in the first register 30, otherwise In the case of a signal from the output of the second prohibition element 28, the information from the first register 30 is overwritten by the second key block 31 into the second register 32. The information recorded in the second register 32 is analyzed in the decoder 33, and a control signal is generated at its corresponding output.

Thus, in a cycle synchronization device, a reduction in the acquisition time corresponding to the duration of one service package is provided.

Claims (2)

1. CYCLE SYNCHRONIZATION DEVICE, comprising a series analyzer of a code, the first element AND, series-connected the first frequency divider, the first inhibit element and the first counter, series-connected the second element AND, the second del- the frequency part, the second inhibit element and the second counter, the clock generator and the distributor connected in series, the output of the clock generator being connected to the clock inputs of the first and second frequency dividers, and the information input of the code analyzer is the input of the device, characterized in that in order to reduce time occurrences of synchronism; an analyzer, service premise, first and second triggers, first and second add-on are introduced into it; AND elements and OR element, while the output of the code analyzer is connected to the first control input of the analyzer of the service parcel, to the combined first inputs of the second element And and the first and second additional elements And to the combined inhibit inputs of the first and second inhibit elements, the clock and second control the inputs of the analyzer of the service parcel are connected respectively to the outputs of the clock generator and the distributor, and the information input of the analyzer of the service parcel of the subkeys to the information input at the code analyzer, the output of the analyzer of the service package is connected to the combined installation inputs of the distributor, code analyzer and the first and second frequency dividers, the output of the first frequency divider is sub-, connected to the second input of the first additional element And, the output of which is through the first counter and - § the OR moment is connected to the enable input of the distributor, the output of the second frequency divider is connected to the second input of the second additional AND element, the output of which is connected to the other input through the second counter OR element, the outputs of the first and second inhibit elements are connected respectively to the inputs of the 1 ”installation of the first and second triggers, the 0 installation inputs of which are connected respectively to the additional outputs of the first and second frequency dividers, the direct outputs of the first and second triggers are connected respectively to the second inputs of the first and second elements And, the inverse output of the first trigger is connected to the third input of the second element And, and the output of the first element And is connected to the enable input of the first frequency divider. 2. The device according to claim 1, characterized in that the service parcel analyzer subsequently contains 1172053 first connected key block, first shift register, second key block, second shift register and decoder, the first AND element, the OR element, and the counter connected in series the first element is NOT and the second element is AND, as well as the third shift register, the first and second inhibit elements, the second and third elements are NOT, and the third element AND, and the clock input of the third shift register is connected to the combined first input m of the first element And and the first element of the ban and the second input of the second element And, the outputs of the first M bits of the third shift register are connected to the M information inputs of the first block of keys, output j is the (M + 1) -th discharge of the third shift register connected to the input of the second element NOT and to the second input. the first element AND, the output of the (2M + 1) -th discharge of the third shift register: connected to the input of the first element NOT and to the third input of the first element AND, the input of the third element NOT and the fourth input of the first element AND are connected to the output of the first discharge of the third shift register, the outputs of the second and third elements are NOT connected respectively to the second and third inputs of the second element AND, the output of which is connected to another input of the OR element, the second input and output of the first inhibit element are connected respectively, to the output of the OR element and the input '' Reset counter, the output of which is connected to the control input of the first block of keys, the control inputs of the first shift register and the second block of keys are connected with responsible for the outputs of the third element And and the second inhibit element, while the combined * first inputs and the combined second inputs of the third element And and the second inhibit element are the first and second control inputs of the analyzer, respectively, the clock and information inputs of the third shift register are clock and information The inputs of the decoder are the outputs of the analyzer.