SU1168956A1 - Device for analysing operation of operational system - Google Patents

Abstract

A DEVICE FOR ANALYSIS OF OPERATION SYSTEM WORK, containing a group of prohibition elements, input register, OR elements, groups of delay elements, AND, OR, element groups, current value registers, comparison blocks, program name registers, triggers, switch, time signal setting unit and the name counter whose bit outputs are the output of device calls, the outputs of the prohibition elements of the input group are connected to the information input of the input register, the setting input of which is connected to the output of the first element OR, the first inputs of the prohibition of the input group are connected to the first information input of the device, the second inputs to the input of the prohibition of the device, the outputs of the bits of the input register are connected respectively to the inputs of the delay elements of the input group, the output of the second element OR is connected to the single inputs of the trigger and the installation inputs current value registers, the outputs of the i-ro bits of the current value register are connected to the first input of the i-ro comparison block (i 1,2, ..., N, where N is the number of program names fixed simultaneously) to The i-ro input of the comparison unit is connected to the output of the i-ro bits of the program name register, the output of each comparison unit is connected to the corresponding inputs of the first OR element, the switch and the zero input of the i-th trigger, the outputs of the i-th group prohibition elements are connected to the information the input of the i-ro register of program names, the outputs of the bits of which are connected respectively to the inputs of the rth element OR (r 3,4, ..., N + 2), the output of which is connected to the first inputs of the prohibition elements of the i-th group, 1- The first output of the first group of outputs of the switch is connected to the first at the counting input of the i-ro counter, the i-th output of the second group of outputs of the switch is connected to the i-th input of the time signal setting block, (N -1г1) -th input of which is the enable input of the device, and the i-th output is connected to the second the counting input of the i-ro counter, whose information input is connected to the outputs of the elements And the i-th input group, whose inputs are connected to the second information input of the device, the outputs of the i-th bits of the counter under (L are connected to the first inputs of the elements And the i-th output group, to the second inputs of which the reading input is connected The devices, the outputs of the elements and output groups are the information outputs of the device, the installation inputs of the initial state of the input register and the program name registers are connected to the installation input of the initial state of the device, the output of the elements of the i-th group, except for N-th, oo, are connected respectively with inputs of delay delay elements (i + l) -th group, with information input (i4-1) -th register of current values and with second inputs of prohibition elements

Description

groups, the second inputs of which are connected to a single output of the i-ro trigger, characterized in that, in order to reduce the analysis time, the groups of AND, OR, name registers, ILINE and decoder elements are entered into it, the inputs of which are connected respectively to the outputs of bits input register, each output of the decoder is connected to the first inputs of the AND (; N + j) -fl elements of the group (jl, 2, ..., L) and (N + L + + 5) -th group (8 1,2 ,. .., L), the third information input of the device is connected to the second inputs of the And (N + j) -ft group elements, the output of each And (N + j) element and the connection groups n with the information input of the corresponding name register, the installation input of which is connected to the installation input of the initial state of the device, the bits of each register of the names are connected respectively to the second inputs of the AND (S + 1 + 5) -th group of elements, the outputs of which are connected respectively to the inputs the OR elements of the first group, the outputs of which are connected respectively to the inputs of the OR-NOT elements and to the first inputs of the OR elements of the second group, the outputs of the OR-NOT elements are connected to the first inputs of the AND (N + 21 + 1) -th group elements, to the second the inputs of which are connected to the outputs of the delay elements of the input group, the outputs of the elements AND (S + 21 + 1) -th group are connected respectively to the second inputs of the elements OR of the second group, the outputs of which are connected respectively to the inputs of the second element OR and the delay elements (L +1) - th group.

The invention relates to computing and can be used in systems for collecting statistical data on the operation of the operating system (OS) programs.

The purpose of the invention is to reduce the analysis time.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2- functional block diagram of setting time signals; in fig. 3 - the switch circuit is functional.

The device contains a group of 1 prohibition elements, a register of 2 inputs, a decoder 3, a group of elements AND 4, registers 5 names, a group of elements AND 6, OR 7, OR-NO 8, AND 9, OR 10, a group of delay elements 11, an element OR 12 , a group of elements And 13, a group of elements 14 of the ban, a group of elements OR 15, And 16, counters 17, a pyppy of delay elements 18, registers 19 of current values, comparison blocks 20, registers 21 of program names, a group of elements And 22, triggers 23, elements 24 delays, block 25 of setting time signals, element OR 26, counter 27 names, element OR 28, switch 29, inputs 30 regis names, inputs 31 counters, read input 32, information output 33 of the device, allowing input 34, output 35 calls, input 36 of the input register and program name registers, information input 37 of the device, prohibition input 38, triggers 39, AND 40 elements switching contact 41, contacts 42 of the first position and contacts 43 of the second position, a coarse time signal generator 44 and a time signal generator 45 switching

contacts 46, contacts 47 of the first position, contacts 48 of the second position.

The device operates as follows. In the initial state, the registers 21 of the program names and the counters 17 are reset. Resetting the program name registers and the input register is performed by applying a single signal to input 36, the counters 17 are reset by input 31, the name registers are input 36, then the names of programs with alternative names are entered into the corresponding name registers, the unused registers remain zeroed.

At the entrance 37 to the inputs of the group of elements 1 of the ban, multi-digit codes of the names of the OS programs arrive on the computer. If the one-bit flag of the analysis of an OS program coming from a computer to the input of a group of prohibition elements 1 has a single value (data on the access to this program need not be collected), the code of the OS program name is lost. If the sign of analysis of the OS program is zero (the program data should be collected), the code of the program name from the output of the group of prohibition elements 1 goes to register 2. The code of the program name from the output of register 2 goes to the decoder 3, which, in accordance with the code of the program name generates a signal at the t-th output, arriving at the inputs of the E-th group of elements And 6 and allowing the program name code contained in the 1st register 5 to pass through this group. From the output of the 1st group of elements And 6 it enters the inputs of the OR elements 7, from the output to through the group of elements OR 10 enters the inputs of the delay elements 18 and the element OR 12. In the case when the code of the input name has no alternative names or they are unknown, the output of the group of elements OR 7 is the zero information that arrives at the inputs elements OR-NOT 8, a single signal is generated at the output, which is fed to the inputs of elements AND 9 and allows the input code of the program name to pass through the groups of elements AND 9 and OR 10, the delay time of elements 11 is chosen equal to the identification time of the alternative and Yeni. The program name code, which arrives at the inputs of delay elements 18 and the OR elements 12, generates at the output of the OR element 12 a single signal, which sets all the flip-flops 23, preparing the operation of the group of elements AND 22, into the unit state. the program (the delay time is chosen so that, before receiving the code of the program name, zeroing of the current value registers 19) is provided to the i-th register 19 of the current values and to the inputs of the i-th group of prohibition elements 14. The inputs of the i-th group of prohibition elements 14 receive a zero signal from the output of the 1st element OR 15 (since register 21 is in the zero state), allowing the reception of the program name code through the 1st group of prohibition elements 14 to the register 21 of program names. After receiving the program name code in the 1st registers 19 and 21, the 1st comparison unit 20 outputs a single signal to the 1st input of the switch 29, to the zero input of the 1st trigger 23 and to the input of the switch 29, to the zero input i- ro trigger 23 and the input of the element OR 28 to reset the register 2. The trigger 23, set to the zero state, prohibits the promotion of the program name code through the i-th group of elements AND 22. Through the switch 29 set to the second position ("Frequency mode a) the single signals from the outputs of the comparison units 20 and the corresponding contacts 46 and 48 are supplied to moves the first group of switch outputs. The signal from the i-ro output of the first group of switches 29 switches into the 1st counter 17 units. Upon further receipt of new codes of program names, an alternative to them is also first analyzed. If they are alterative, then from the corresponding register 5 it is chosen that is unique to them, which enters the analysis scheme. If it is not fixed in register 21, then free registers 21 are sequentially occupied, which is ensured by the installation of the flip-flops 23 in one state. If all the registers are occupied, and register 2 receives a program name code that is not equal to the program name codes stored in registers 21, then this code, passed successively through N groups of delay elements 24 and groups of elements 22, enters the inputs of the element OR 26. At the output of this element, a single signal appears, which increases by one the contents of the name counter 27 and zeroes the OR register 28 element 2. Thus, in the name counter 27, the number of program calls that are not stored is fixed region ters 21 program names. If the input of the register 2 is the code of the program name, which already exists on one of the registers 21 of the names of the programs, for example, with the number i (1 i N), then this code is not written into the other free register 21, but only is compared with the code on the block 20 comparison and a single signal from the output of the comparison unit 20 is fed to the input of the switch 29. The signal from the output of the first group of outputs of the switch 29 increases the value of the 1st counter 17 by one. If it is necessary to measure the transit time of any program, the switch 29 switches to the first position ("Time Mode"). In this case, single signals from the outputs of the comparison units 20 through the switching contacts 46 and the contacts 47 of the first position arrive at the output of the second group of outputs of the switch. When a single signal occurs at the output of the second group of outputs of the switch 29, the i-th trigger for switching on the time signals of the block 25 is set to one, as a result, the i-th element I is prepared for operation and through it the i-th counter 17 begins to receive time signals After the end of the program execution, the on-input signal 34 sets the on-time triggers to the zero state. As a result, the program execution time is recorded in counters 17. Through groups of elements AND 16, 31 counter codes are entered from the input. These codes come from a computer and represent the number of calls to specific OS programs when a pre-existing task stream is executed on a computer. The need for such entry of codes arises when collecting generalized data on the operation of OS programs when passing through a computer various task streams in a fixed time. The output of data from the device is carried out through groups of elements AND 5 according to the signal arriving at input 32.

After collecting data on the access to OS programs with N unique names, it is advisable to prohibit the further collection of data about these programs by making signs of the analysis of these programs using a special auxiliary program.

The OS is equal to one and rebuilding the contents of the registers 4. In this way, data is already being collected about other OS programs that are accessed from the task stream of users and whose analysis features are zero.

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Claims (1)

DEVICE FOR ANALYSIS OF OPERATING SYSTEM OPERATION, which contains prohibition element groups, input register, OR elements, delay element groups, AND, OR element groups, counters, current value registers, comparison blocks, program name registers, triggers, switch, time signals and a name counter whose discharge outputs are the output of device calls, the outputs of the input group inhibition elements are connected to the information input of the input register, the installation input of which is connected to the output of the first OR element, the output inputs of the input group inhibit elements are connected to the first information input of the device, the second inputs are connected to the device inhibit input, the outputs of the input register bits are connected respectively to the inputs of the input group delay elements, the output of the second OR element is connected to the single inputs of the triggers and to the setting inputs of the current value registers , the outputs of the bits of the ί-th register of current values are connected to the first input of the i-ro comparison block (i = 1,2, ..., N, where N is the number of program names recorded simultaneously), to the second input the outputs of the bits of the i-ro register of program names are connected to the i-ro block of the comparison, the output of each comparison block is connected to the corresponding inputs of the first OR element, the switch, and to the zero input of the i ^: th trigger, the outputs of the i-group inhibit elements are connected to the information input i -ro of the register of program names, the outputs of the bits of which are connected respectively to the inputs of the ith element OR (r = 3,4, ..., N + 2), the output of which is connected to the first inputs of the ban elements of the i-th group, i-th the output of the first group of outputs of the switch is connected to the first counting input to the i-ro counter, the i-th output of the second group of outputs of the switch is connected to the i-th input of the unit for setting time signals, (N +1) -th input of which is the enabling input of the device, and the i-th output is connected to the second counting input i -ro counter information input coupled to the outputs of the AND i-th input group, whose inputs are connected _with second information to cheny Valid Device for SS roystva, bits i-ro outputs of the counter are connected to first inputs of AND i-th output of the group , to the second inputs of which the reading input of the device is connected, the outputs elements and output groups are the information outputs of the device, the inputs of setting the initial state of the input register and registers of program names are connected to the input of setting the initial state of the device, the outputs of the elements of the i-th group, except the N-th group, are connected respectively to the inputs of the delay elements (i + 1 ) of the group, with the information input (ifl) -ro of the register of current values and with the second inputs of the elements of the prohibition of the (i + 1) -th group, the outputs of the elements of the Nth group are connected respectively to the inputs of the (N + 3) -ro of the element OR whose output is connected to the midrange to the input of the name counter and to the corresponding input of the first OR element, the outputs of the delay elements (N-bl) -fi groups are connected to the inputs of the delay elements of the first group, with the information input of the first register of current values and with the second inputs of the elements of the first group inhibit, outputs of the delay elements The i-th group is connected to the first inputs of the elements And the i-th SU. the inputs of which are connected respectively to the outputs of the bits of the input register, each decoder output is connected to the first inputs of the elements of the And (N + j) -fl group (j = l, 2, .. „L) and (N + L + + S) -ft of the group (S = 1,2, ..., L), the third information input of the device is connected to the second inputs of the elements of And (N + j) -fl groups, the output of each And (N + j) -th group connected to the information input of the corresponding register of names, the installation input of which is connected to the input of the installation of the initial state of the device, the outputs of the bits of each name register are connected respectively to the second inputs of the elements And (N + L + S) -ft groups, the outputs of which are connected respectively to the inputs of the elements OR of the first group, the outputs of which are connected respectively to the inputs of the elements OR — NOT and to the first inputs of the elements OR of the second group, the outputs of the elements OR — NOT connected to the first inputs of the elements AND (N + 2L + l) -ft groups, to the second inputs of which the outputs of the delay elements of the input group are connected, the outputs of the AND (N + 2L +1) elements of the group are connected respectively to the second inputs of the OR elements of the second group, the outputs of which are connected respectively to the inputs of the second OR element and the delay elements (N + l) -fl group.