SU1150764A1 - Frequency synthesizer - Google Patents

Abstract

1. A FREQUENCY SYNTHESIZER containing a series-connected phase detector, a first stable current generator, a low-pass filter, a controlled oscillator, a variable divider frequency divider, a first key and a shift register, the first output of which is connected to the R input of an RS flip-flop, whose output connected to another input of the first key, the second stable current generator, the input and output of which are connected respectively to another output of the phase detector and an input of a low-pass filter connected in series A fixed generator and a frequency divider with a fixed division factor, as well as a code converter, the code inputs of which are connected to the corresponding code sensor outputs, the setup inputs of a frequency divider with a variable division factor connected to the corresponding code outputs of the code converter, characterized in that in order to improve the spectral purity of the output signal and reduce the tuning time, a second switch and an inverter, a third switch, and the first and the second AND-OR elements, whose elevations are connected to the corresponding inputs of the phase detector, the first input of the first AND-OR element, the first bypass of the second AND-OR element and the first input: the third key is combined and connected to the output of a frequency divider with a fixed division factor, the second input the first element AND-OR is combined with the second input of the second element AND-OR and connected to the output of a frequency divider with a variable division factor; the first control inputs of the first and second elements are AND-OR under (L are connected respectively to the inspector's output and the output of the second key, the second control inputs of the first and second AND-OR elements are connected respectively to the output of the second key and the inverter output, the first and second inputs of the second key are connected respectively to the second output of the shift register and to the information sl output code converter, the first O) control input of which is combined with the D input of the shift register and connected to the output of the R $ trigger, the second control input of the code converter is combined with the 5 input of the R5 trigger and is connected to the set th output code sensor, the third control input of the code converter is combined with the reset input of the shift register and is connected to the output of the third switch, the second input of which is combined with the reset input of the frequency divider with dividing factor paremennym and connected to the first output of the shift register.

Description

2. A synthesizer according to claim 1, wherein the code converter comprises a serially connected storage unit, an intermediate division coefficient calculation unit and a switching unit, wherein the second group of inputs of the switching unit, the second group of inputs of the intermediate division coefficient calculation unit and the code inputs of the memory unit are combined and are the code inputs of the converter 50764

l codes, the outputs of the switching unit. are the code outputs of the code converter, the control units (the inputs of the switching unit, the intermediate division coefficient calculation unit and the storage unit are the first, second and third control inputs of the code converter, respectively, and the information output of the intermediate ratio calculation unit is information output of the code converter.

The invention relates to radio engineering and can be used to generate a frequency grid in wide-field transmitters and receivers.

A known frequency synthesizer, serially connected reference oscillator, first frequency divider with variable division factor, phase detector, controlled oscillator, second frequency divider with variable division factor, synchronization sensor, counter and code converter, the output of which is connected to the setup input of the second frequency divider with a variable division factor, the output to the second one is also connected to another input of the synchronism sensor, as well as a code sensor, the outputs of which are connected to the second to the inputs of the counter and code converter, the counter code is connected to the installation input of the first frequency divider with a variable division factor Cll.

However, the spectral purity of the output oscillations of such a synthesizer is not high enough due to the need to expand the passband of the low-pass filter included in the phase detector, due to a change in the frequency of the comparison during the tuning process over the range.

Closest to the present invention is a frequency synthesizer containing a series-connected phase detector, a first stable current generator, and a low-pass filter.

controlled oscillator, variable frequency divider, first key and shift register, the first output of which is connected to the R input of the RS flip-flop, the output of which is connected to another input of the first key, the second stable current generator, the input and output of which are connected respectively to another the output of the phase detector and the input of a low-pass filter, a series-connected reference oscillator and a frequency divider with a fixed division factor, as well as a code converter, the code inputs of which are connected to to the corresponding outputs of the code sensor, the frequency dividers setting inputs with a variable division factor are connected to the corresponding code outputs of the code converter Cz.

However, the tuning response and spectral purity of the output signal of this frequency synthesizer are not high enough.

The purpose of the invention is to increase the spectral purity of the output signal and reduce the tuning time.

This goal is achieved by having a frequency synthesizer containing a series-connected phase detector, a first stable current generator, a low pass filter, a controlled oscillator, a variable division factor frequency divider, a first key and a shift register, the first output of which is connected to the R input of RS -trigger, the output of which is connected to another input of the first key, the second stable current generator, the input and output of which are connected respectively to another output of the phase detector and the input of the lower frequency filter, pos consecutively connected generator and frequency divider with a fixed division factor as well as a code converter, the code inputs of which are connected to the corresponding outputs of the code sensor, the setting inputs of a frequency divider with a variable division factor connected to the corresponding code outputs of the code converter, the serially connected second ones are entered the key and the inverter, the third key, as well as the first and second elements of the AND-OR outputs of which are connected to the corresponding (they are the inputs of the phase detector, the first in the stroke of the first AND-OR element, the first input of the second AND-OR element and the first input of the third key are combined and connected to the output of a frequency divider with a fixed division factor, the second input of the first AND-OR element is combined with the second input of the second AND-OR element and connected to the output of the frequency divider with a variable division factor, the first control inputs of the first and second elements AND-OR are connected respectively to the output of the inverter and to the output of the second key, the second control inputs of the first and second elements AND-OR are connected respectively, with the output of the second key and with the output of the inverter, the first and second inputs of the second key are connected respectively to the second output of the shift register and to the information output of the code converter, the first control input of which is combined with the D input of the shift register and connected to the output of the RS trigger, the second control input of the code converter is combined with the S input of the RS flip-flop and connected to the installation output of the code sensor, the third control input of the code converter is combined with the zero input of the shift register and the connection n to the output of the third switch, the second input of which is combined with the reset input of the frequency divider with a variable division factor, and connected to first output of the shift register. The code converter contains series-connected memory units connected in series, an intermediate division coefficient calculation unit and a switching unit, the second input unit group of the switching unit, the second input unit group of the intermediate division coefficient calculation unit, and the code inputs of the memory unit are combined and are the code inputs of the code converter, outputs the switching unit are code outputs of the code converter, the control inputs of the switching unit, the intermediate division coefficient calculation unit and the storage unit are respectively the first, second and third inputs of the converter by the control codes, and the data output unit for calculating an intermediate coefficient division is code data output transducer. The drawing shows a structural electric frequency synthesizer. The frequency synthesizer contains a reference oscillator 1, a frequency divider with a fixed division factor (DFCD) 2, a phase detector 3, the first stable gok generator 4, a second stable current generator 5, a low-pass filter 6, a control oscillator 7, a frequency divider with a variable division factor (DPKD) 8, code converter 9, sensor code 10, first key 11, shift register 12, second key 13, inverter 14, third key 15 RS-flip-flop 16, first AND-OR element 17, second AND-OR element 18. The code converter 9 contains a switching unit 19, the calculating unit There are 20 intermediate dividing factors, a memory unit 21. The frequency synthesizer operates as follows. In the initial state, the controlled oscillator 7 amplifies the signal with the frequency f ,, set with the help of the division factor N of the PDDK 8 and due to the operation of the phase locked loop. The pulse sequences at the inputs of the phase detector 3 have the same period, repetition and zero phase shift. At the output of the filter 6, there is a constant control voltage. At the control input of the block, switching and signal 19 is absent also to the installation, inputs of the PCD 8 through the switching unit 19 of the converter kbdov 9. A change of the frequency code f from the outputs of the code sensor 10 is transmitted to the change bbz. Consequently, this frequency code is fed to the inputs of the memory unit 21, from the outputs of which the same information is fed to the first inputs of the computation unit 20. The switching frequency of the output oscillations is carried out as follows. After the set of the new frequency 2 value has been completed, the installation output of the code 10 sensor appears and a pulse of the installation appears on the code outputs of the code 10 sensor simultaneously with information on the new value of the frequency f,. The setup impulse includes a converter calculating unit 20 for ids 9, which processes the codes arriving at its inputs, and a level or 0, depending on the sign of the frequency difference f, is set at its information output. At the same time, a pulse from the sensor 10 output goes to the S input of the RS-flip-flop 16 and a level 1 is set at its output, under the action of which the code output of the converter 9 is an intermediate dividing coefficient code that is proportional to the difference between the previous frequency value f,, and the new value fj of the DPCD 8 continues to divide with the initial coefficient N until the end of the division cycle C11 and the appearance of the next pulse at its output. At the end of the division cycle, the DPKD 8 division factor is set. The intermediate division cycle begins, which is necessary for the pulses from the DFCD 2 and DCD 8 outputs to appear at the inputs of the phase detector 3 in the sequence and with the delay necessary for the new voltage control value corresponding to the set frequency fg to form by the phase detector 3. In IT, the pulse occurrence sequence and the delay time are determined by the sign and the amount of detuning, respectively. Depending on the detuning sign, with the help of the second key 13, the inverter 14 and the first and second elements 17 and 18, the inputs of the phase detector 3 are connected either to the DCDD 8 and DCDD 2 OR, on the contrary, to the DCDD 2 and DCD 8, respectively. Switching the inputs of the phase detector 3 is realized by the signal 1 from the second output of the shift register 12 at the end of the last division cycle of the DPDD 8 with the initial coefficient N. With the appearance of a pulse at the output of the DPC / J 8 in the intermediate 1 click the division at the first output of the shift register 12 through is level 1, which blocks PDCD 8, and at the second output of shift register 12, level O appears. At the outputs of code converter 9, code N2 appears corresponding to the new frequency value fj. The next impulse from the DFCD 2 output goes, depending on the detuning sign, either to the first or to the second inputs of the phase detector 3 and at the same time to the second input of the third key 15, at the output of which a signal appears that records information about the new frequency fj in the block 21 of the code converter 9. At the same time, the lock is released from the PDKD 8 and a new division cycle starts with division factor N. The algorithm of the conversion 9 functions is described by the expression of the period of the comparison frequency; the division ratio of DCPD 8; equivalent control steepness of the controlled generator 7 (values and and Uj are determined by the control characteristic (U) of the controlled generator 7 stored in the computation unit 20); h the equivalent slope l4-iiJ of the conversion characteristic of the phase detector 3. The values of t and t are determined by the conversion characteristic (-t) recorded in calculation unit 20. Each value of the control voltage at the output of phase detector 3 corresponds to a certain value of the time delay. The sign of the rearrangement is determined by the sign of the difference. . . The relationship between the frequencies of the output signals f and f and their corresponding DPKD division factors N and N is described by the expressions M. to Thus, in the proposed frequency synthesizer, when rebuilding, the mismatch is processed in one comparison period without changing the comparison frequency. The error in setting the new control voltage is not significant and is being processed by a phase locked loop. Since the change in the control voltage during the rearrangement occurs continuously, and the power of this process can reach one period TO, the speed at which the control voltage changes is much less important than in the prototype and therefore it becomes possible to use filter 6 more constant, which will increase the spectral purity of the output signal.

Claims (2)

1. FREQUENCY SYNTHESIS comprising a phase detector in series, a first stable current generator, a low-pass filter, a controlled oscillator, a frequency divider with a variable division ratio, a first key and a shift register, the first output of which is connected to the R input of an ^ RS flip-flop, the output of which connected to another Input of the first key, the second stable current generator, the input and output of which are connected respectively to the other output of the phase detector and the input of the low-pass filter, connected in series to the reference a frequency divider and divider with a fixed division coefficient, as well as a code converter whose code inputs are connected to the corresponding outputs of the code sensor, the installation inputs of a frequency divider with a variable division coefficient 'are connected to the corresponding code outputs of the code converter, characterized in that, for the purpose of to increase the spectral purity of the output signal and reduce the tuning time, the second key and the inverter, the third key, and also the first and second element are subsequently connected s AND — OR, the outputs of which are connected to the corresponding inputs of the phase detector, the first input of the first AND-OR element, the first input of the second AND-OR element and the first input: of the third key are combined and connected to the output of the frequency divider with a fixed division ratio, the second input of the first The I-IPI element is combined with the second input of the second AND-OR element and connected to the output of the frequency divider with a variable division ratio, the first control inputs of the first and second AND-OR elements are connected respectively to the inverter output and to the output of the second key, the second control inputs of the first and second AND-OR elements are connected respectively to the output of the second key and to the inverter output, the first and second inputs of the second key are connected respectively to the second output of the shift register and to the information output of the code converter, the first control input of which combined with the D input of the shift register and connected to the output of the RS-trigger, the second control input of the code converter is combined with the 5 input of the RS-trigger and connected to the installation output of the code sensor, the third control yuschy code converter input is combined with the reset input of the shift register and is connected to the output of the third switch, the second input of which is combined with the reset input of the frequency divider with a variable division factor and Con chen to first output of the shift register. 2. The synthesizer according to claim 1, wherein the code converter comprises sequentially connected storage unit, an intermediate division coefficient calculation unit and a switching unit, the second group of inputs of the switching unit, the second group of inputs of the intermediate division coefficient calculation unit and the code inputs of the storage unit are combined and are the code inputs of the code converter, the outputs of the switching unit. are the code outputs of the code converter, the control inputs of the switching unit, the intermediate division coefficient calculation unit, and the memory block are the first, second, and third control inputs of the code converter, and the information output of the intermediate division coefficient calculation unit is the information output of the code converter.