SU1105897A1 - Device for checking logic units - Google Patents

Abstract

A DEVICE FOR THE CONTROL OF LOGICAL BLOCKS, containing a test setter, a control unit, a pulse generator, a group of f, signature analyzers (where n is the number of device information inputs) and a display unit, the control unit contains the first, second and third triggers, the first element OR , the first counter, the first element is NOT, the first element is And and two switches, with the outputs of the first and second switches are connected respectively to the inputs of the first and second triggers of the control unit, the unit output of the first trigger The control unit is connected to the first input of the first OR element, the output of which is connected to the initial input of the first element, the unit output of the second trigger of the control unit is connected to the zeroing input of the first counter of the control unit, to the initial settings of the signature analyzers of the group, the overflow output of the first counter is connected to the counting input of the third trigger, the zero output of which is connected to the second input of the first element I and, through the first element of the control unit NOT, to the recording resolution input For each group signature analyzer, the information output i 1 + 1) of the signature analyzer is connected to the input of the display unit, the information outputs of the test unit are the test outputs of the device, each input of the group of information inputs of the device is connected to. the first information input of the corresponding group signature analyzer, the information output of each i-ro signature group analyzer (where i- from 1 to n) is connected to the second information input (-1 4-1) of the signature analyzer, the second information input of the first I signature analyzer connected to a zero-potential bus, so that, in order to increase the speed, the device has an adjustable delay block containing a register, a counter, an AND element and an OR element, and four controllers are entered into the control unit. Rotary and fifth triggers, second counter, group of switches, second and third elements AND, second OR element and second element NOT, and the zero output of the third trigger of the control unit is connected to the first input of the second element AND whose output connects is not connected with the counting input of the first counter of the control unit and with the clock input of the test setter, the output of the first element I is connected to the counting input of the fourth trigger, the unit output of which is connected to the second input of the second element I of the control unit The unit I. block of the adjustable delay and with the counter resolution input of the block of the adjustable delay, the single output of the second trigger of the control unit is connected to the first input of the second OR element, to the initial installation input of the second counter, the overflow output of which is connected to the second input of the second OR element, ; xo the second element OR is connected

Description

with the input of the initial setup of the third trigger, the unit output of which is connected to the first input of the third element I and through the second element NOT to the start input of the first i signature group analyzers, the output of the clock generator.connected to the second input; the third element I of the control unit and to the second input of the element And the block of the adjustable delay, the output of the third element And the control unit is connected to the counting input of the second counter, with the input of the census resolution in 1p + 1) -th signature analyzer group, with the first input of the IL element the tunable delay unit, the outputs of the third switch of the control unit are connected respectively to single and zero, the inputs of the fifth trigger of the control unit, the unit output of which is connected to the write enable input of the register of the adjustable delay unit, the information outputs of which are connected to the information inputs of the counter, the output And customizable unit the delay is connected to the counting input of the counter, the overflow output of which is connected to the second input of the OR element of the tunable delay block, from the input th first OR control unit and to the input of the initial setting of the third flip-flop control unit, an output of OR adjustable delay unit coupled to the clock input of the first n signature analyzers group control unit outputs a group of switches are connected to the data inputs of the adjustable delay unit register.

one

The invention relates to computing and can be used to control logic blocks of electronic digital equipment.

A device for controlling logic blocks is known, which operates according to the principle of comparing reference output reactions with output reactions obtained at the outputs of the controlled block. It contains a memory, a recording unit, a pulse generator, a trigger, the first and second elements AND, a control unit, a pulse counter, a decoder, a test register, a switch, and a logic state comparison circuit l.

The disadvantages of this device are:.

relatively low speed due to the use of the memory as a test generator and due to the sequential change of input actions in order to eliminate the races of electrical signals in the circuit;

a large amount of memory used for storing test, program and reference output reactions.

Closest to the present invention is a device for monitoring logic blocks, comprising a test setter, a controlled logic block, a control unit, a pulse generator, first n signature analyzers, a second signature analyzer, and a display unit. The outputs of the control unit are connected to the first inputs of signature analyzers and to the input of the test setter, the outputs of which are connected to the inputs of the monitored unit, the outputs of which are connected to the second inputs of the first n-signature analyzers, the output of each previous one of the first n signature analyzers is connected to the third input of each subsequent one the first and signature analyzers, the input of the last nth signature analyzer is connected to the input of the second signature analyzer, the output of which is connected to the indicator unit of

The control unit contains three flip-flops, the first AND element, the first inverse of the OR element, the first counter, two switches that switch the setup inputs of two triggers, and the output of the first trigger through the OR element is connected to the first input of the first element And, the output of the second trigger is connected to the input reset the first counter 23.

A disadvantage of the known device is that it can only control the logic blocks containing the circuits, the limiting frequency

work which is less than or equal to the fixed frequency of the device. This leads to the occurrence of indefinite states of these schemes, which ultimately leads to ambiguity of the output signatures.

Another disadvantage of this device is the relatively low speed in monitoring logic blocks, in which the propagation time of signals from input to output is shorter than the fixed time in the control device. the control of one block by the device is determined by the delay time of the signal from input to output. When monitoring blocks / for which the time of signal propagation from the input to its output is short, (the performance of the device for control drops, since the fixed time required for reading the signature does not change when controlling blocks that have less time for control. The invention is an increase in the speed of a control unit of a logic block. The goal is achieved by the fact that a block of tunable delay is inserted into a device for controlling logic blocks, containing a register, a counter, an element t I and OR, and the fourth and fifth triggers, the second counter, the switch group, the second and third AND elements, the second OR element, and the second element NOT, and the zero output of the third trigger of the control unit are connected to the first input element I, the output of which is connected to the counting input of the first counter of the control unit and to the clock input of the test setter, the output of the first element I is connected to the counting input of the fourth trigger, whose single output is connected to the second input of the second element AND control, with the first input of the element And the block of the adjustable delay and with the count resolution enable input of the block of the adjustable delay, the unit output of the second trigger of the control unit is connected to the first input of the second OR element, to the input of the initial installation of the second counter, the overflow output of which is connected to the second input the second element OR the output of the second element OR is connected to the input of the initial installation of the third trigger, the unit output of which is connected to the first input of the third element AND and through the second element NOT with the start input of the first n signature analyzers of the group, the output of the clock generator is connected to the second input of the third element I of the control unit and the second input of the element I of the tunable delay unit, the output of the third element I of the control unit is connected to the counting input of the second counter, with the enable input. the census in the (n + 1) -and signature-based analyzer of the group, with the first input of the OR element of the tunable delay unit, the outputs of the third switch of the control unit are connected respectively to the single and zero inputs of the fifth trigger of the control unit / whose single output is connected to the input. register entries of the tunable delay block, whose information outputs are connected to the information inputs of the counter, the output of the AND block of the configurable delay block is connected to the counting input of the counter, the overflow output of which Connected to the second input of the OR unit of the adjustable delay, to the input of the first OR element of the control unit and to the input of the initial installation of the third trigger of the control unit, the output of the OR unit of the adjustable delay is connected to the clock input of the first n signature analyzers, the outputs of the switch group of the control unit group are connected to information inputs of the register register custom delay. FIG. 1 shows a block diagram of a device for monitoring logical blocks; in fig. 2 is a functional block diagram of the control unit; in fig. 3 functional block diagram customizable delay. The device for controlling logical blocks contains a control block 1, a bus 2 control signals 2.12 (+7), a generator of 3 pulses with output 4, a block 5 of adjustable delay with outputs 6.1, 6.2, a setting unit 7 of tests, generating test sequences at outputs 8 and is a pseudo-random code sequence generator, a controlled logic block 9 with outputs 10.1 - 10.h, first 11 and second 12 elements AND, elements 13 OR, modulo-two adders 14 and shift registers 15, forming a group of signature analyzers 16.1-16. and having Exit 17.1-17.p, the signature analyzer 18 containing an adder 14, a register 15 and the display unit 19. The outputs of the control unit 1 are connected to the inputs of elements 11 and 12 and the installation input of the signature analyzer group 16.1-16. ri, with the inputs of the block 5, with the inputs of the signature analyzer 18 and with the input of the unit 7 test. The outputs 8 of the test unit 7 are connected to the input w of the monitored unit 9, the outputs 10 of which are connected to the inputs of the adder 14 of the group of signature analyzers 16.1-16.i. The output 4 of the pulse generator 3 is connected to the first input of the control unit 1 and to the input of the unit 5. The output 16.1 of the unit 5 is connected to the second input of the control unit 1. Output 6.2 of block 5 is connected to the gate inputs of the signature analyzer group 16.116 .1. in each signature analyzer 16, the outputs of the adders 14 are connected to the inputs of the And 11 element. The outputs of the And 11 and 12 elements are connected to the inlet.

domi element OR 13, the output of which is connected to the input of the register 15. The outputs of the register 15 are connected to the inputs of the adder 14. The output of the last bit of the register 15 of the previous group 16 is connected, in addition, to the input of the element And 12 of the subsequent group 16, except for the signature analyzer 16, 1, in which the input element 12 is grounded. In the analyzer 16.p, the output of the last bit of the register 15 is connected to the information input of the signature analyzer 18, the output of which is connected to the display unit 19.

The control unit 1 (Fig. 2) contains switches 20-22, switching 15 setting inputs of flip-flops 2325, D-triggers 26 and 27, elements AND 28, OR 29, And 30, And 31, elements 32 and 33, binary pulse counters 34, 35, element OR 36 and a group of 20 switches 37.

The output of the trigger 24 is connected to the reset input of the counters 34, 35 and to the installation input of the trigger 27 via the element OR 29. The output of the trigger 25 23 is connected to the counting input of the trigger 26 through the element OR 36 and the element 30, the output of which is the output 2.4 of the block management The second input element OR 36 and the installation 30 input of the trigger 26 are connected to the input 6.1 of the control unit. The output of the trigger 26 is the output 2.5 of the control unit and, in addition, is connected to the second input of the element 28. The output 35 of the element 28 and is connected to the counting input of the counter 34 and is the output 2.1 of the block 1. The single output of the trigger 27 through the element 32 enters output 2.2 of control unit 40; and through element I 31 - to the counting input of counter 35 and output 2.6 of the control unit.

The zero output of the trigger 27 is connected to the first input element And 28,. the second input of the element I 30 and through the element NO 33 - with the output 2.3 of the control unit.

The output 4 is connected to the second input of the element AND 31. The output of the overflow of the account.Ike 35 is connected to the second input of the element OR 29. The overflow output of the counter 34 is connected to the counting input of the trigger 27.

The block 5 of the adjustable delay (Fig. 3) contains an element AND 38, an element 55 or 39, a register 40, and a reversible counter 41 pulses. The inputs of the element 38 are connected to the inputs 2.5 and 4, and the output is connected to the counting input of the counter 41. The information inputs of register-60 and 40 are connected to the outputs 2.7-2 (+7) of lock 1, and the outputs are connected to the information inputs of the counter 41, output which is connected to the first input of the element OR 3 9 and output 6.1 5

control unit. The second input element OR 39 is connected to the output 2.6 of block 1, and the output is connected to signal 6.2. The entry entry of the counter 41 is connected to the output 2.5 of block 1,

The device works as follows.

In block 1, signal control 2.4 sets the signature analyzer group 16.1, ..., 16 .ti and signature analyzer 18 to their initial state by signal 2.7. In block 5 of the adjustable delay, the time delay code is written (signals 2.8, ..., 2 (2 + 7} propagation of binary signals through the monitored block 9. The delay is set using a group of switches 37 in the control block 1. On the control signal 2.1, the setpoint generator 7 outputs the first test, which goes to the inputs of the monitored block 9.

From outputs 10.1, ..., 10.P, the information 1 responds to the incoming information of the first test through adders 14, performing a modulo-two addition operation, through AND 11 elements and OR 13 elements to the inputs of shift registers 15. - A single value of signal 2. 2 and zero value of signal 2.3 open elements 11 and close elements 12, respectively. Signal 2.5 from the control unit triggers an adjustable delay unit 5, which outputs a signal 6.2 to record information from the outputs of block 9 into the first sections and shift registers 15, each of which has tn bits. At this time, the shear pulses 2.6 do not enter the analyzer 18.

Then a second test is issued.

Block 1 of control by signal 2.5 turns on block 5 again. delay, which repeats the action of writing to registers 15 (taking into account feedbacks through adders 14 of information received from outputs 10.1 ,, .. ..., 10. g of block 9. As a result of passing the entire program (sequence of tests) in registers 15 of the shift, the output information of the controlled 9 block is recorded per channel in the form of a signature.

After passing all the tests, the control unit 1 closes the AND 11 element and opens the AND 12 element and generates a sequence of pulses hm (signal 2.6 and 6.2) of the shift, through which signatures formed in registers 15 are transmitted through elements 12 and 13 from registers of previous signature analyzers to subsequent registers and from the last n-th signature analyzer to analyzer 18, where a resultant signature is formed for the monitored 9 block. This signature is the compressed information from the output response of the monitored block to the input test sequence. The signature is indicated by the display unit 19. The operator compares the received signature with the reference one calculated for the healthy logic block, and, in accordance with the comparison result, judges the health of the monitored block. Block 5 custom delay works as follows. At the beginning of the control process by pressing the button switch Zag 22, FIG. 2) at the output of the trigger 25 (the signal 2.7 of the control unit I appears a clock pulse that enters the register 40, writes the time delay code for the monitored block, set using tumbler switches 37 The time delay is stored in this register until the end of the process control. When the signal 2.5 goes from the level to the unit level, the contents of register 40 are rewritten into the reversible counter 41, and the element 38 is opened, which allows the sequence 41 to send a pulse to the counting input of the counter 41 in from generator 3. In this case, a count is made until the counter overflow signal 6.1 (indicating the expiration of the specified delay) is used to write to the shift registers 15. When a resultant signature is formed in a group of n signature analyzers, a sequence of shift pulses 6.2 enters into registers 15 from generator 3 in the form of a signal 2.6 through an OR element 39. The block of adjustable delay allows changing the sampling frequency in the range from / 2 to {p, where fr is the frequency of the pulse generator} e is the counter size 41. The delay in monitoring a certain logic block is specified by a group of switches 37 of the control unit. This code determines the frequency of gating and is computed as the nearest large integer resulting from dividing the time delay of propagation of signals through the monitored block by the period If. Oscillator 3. Period T is determined by the total delay of the propagation of signals through elements 1 and 13, adder 14 and shift register. This frequency is fixed and depends only on the element base used in the proposed device. Control unit 1 operates as follows. After pressing the button 21 Suit. the impulse from the trigger output 24 resets the trigger 27, the counters 34, 35 and signature analyzers 16.1 -16.p and 18. The zero state of the trigger 27 allows the signals to pass through the element 30, opens the HE element 32 by means of the HE element 32 And 2.2 and locks through the element NOT 33 by signal 2.3 elements 12 AND analyzers 16.1, ..., 16.p. After pressing the Start button 20, the pulse from the trigger output 23 goes through the elements OR 36, And the element 30 sets the trigger 26 to 1, the output of the trigger 26 (signal 2.5), as indicated, starts the block 5 of the adjustable delay, output 6.1 of which through feedback is fed to the input of the OR 36 element and to the setup input of the trigger 26, to form a built-in variable frequency pulse generator. The sequence of pulses 2.5 passes through the open element AND 28 (since the trigger 27 is in the zero state), arrives at the counting input of the counter 34 and leaves the control unit 1 as the signal 2.1. The counter 34 counts up to N pulses corresponding to the number of tests. After overflowing from the ether 34, the trigger 27 is set to 1, which locks the element 30 and opens the element 33 through the element 33 and closes the element 11 and closes the element 11. At the same time, the step of submitting tests and sampling channel signatures ends. A single state of trigger 27 opens AND 31. and passes a pulse train from generator 3 to counting input of counter 35. The latter counts the required number of pulses to form a resultant signature in analyzer 18. Pulses from output 2.6 of block 1 pass through block 5 of the adjustable delay ki, is output as a register shift signal 6.2 from the analyzers 16.1, ..., 16. and records to the analyzer 18. The overflow signal of the counter 35 through the OR element 29 clears the trigger 27, which blocks the transmission of pulses through the AND 31 element.indicates the end of the process of forming a resultant signature in the analyzer 18. Last. displayed by the display unit 19. Unlike the prototype, the proposed device allows the control of logical blocks with different delays in signal propagation. If in the prototype for such control it is necessary to replace the delay elements that are in the generator of the gating pulse of the setter (Tests and recordings into the group of w CHrHa analyzers, which is inconvenient with

From the standpoint of device design and time consuming, in the proposed device, by introducing a settable delay unit and modifying the control unit, it is only necessary to record the signal propagation signal code for the object being monitored. Tuning gating frequency and gating

input information in the presence of test data at the circuit inputs eliminates uncertain states in the circuit of the monitored block, causing ambiguity of signatures inherent in the prototype in the control when the limiting frequency of the monitored block is less than fixed in the control device.

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Claims (1)

DEVICE FOR CONTROL OF LOGIC BLOCKS, containing · test drive, control unit, pulse generator, a group of η signature analyzers (where n is the number of information inputs of the device) and an indication unit, 'the control unit contains the first, second and third triggers, the first element OR , the first counter, the first element NOT, the first element AND and two switches, and the outputs of the first and second switches are connected respectively to the inputs of the first and second triggers of the control unit, a single output of the first trigger is bl The control is connected to the first input of the first OR element, the output of which is connected to the first input of the first AND element, the single output of the second trigger of the control unit is connected to the input of resetting the first counter of the control unit, to the inputs of the initial installation of the signature analyzers of the group, the overflow output of the first counter is connected with the counting input of the third trigger, the zero output of which is connected to the second input of the first AND element and through the first element NOT of the control unit - with the input of recording permission, recording of each signature polar groups analyzer information output ί n + 1) th signature analyzer connected to the input unit, see indications. the information outputs of the test setter are test outputs ^; properties, each input of the group of information inputs of the device is connected to the first information input of the corresponding signature analyzer of the group, the information output of each i-ro signature analyzer of the group (where i is from 1 to p) is connected to the second information input of the (-ί + 1) -th signature analyzer , the second information input of the first! signature analyzer is connected to the zero potential bus, characterized in that, in order to improve performance, a custom delay unit containing a register is inserted into the device uk, an AND and an OR gate, and a block. The fourth and fifth triggers, the second counter, the group of switches, the second and third AND elements, the second OR element and the second NOT element are introduced, and the zero output of the third trigger of the control unit is connected to the first input of the second AND element, the output of which is connected to the counting input of the first the counter of the control unit and with the clock input of the test setter, the output of the first element And is connected to the counting input of the fourth trigger, the single output of which is connected _? with the second input of the second AND element of the control unit, with the first input of the AND element of the custom delay unit and with the counter enable input of the custom delay unit counter, the single output of the second trigger of the control unit is connected to the first input of the second OR element, with the input of the initial installation of the second counter, output the overflow of which is connected to the second input of the second OR element, the output of the second OR element is connected to the input of the initial installation of the third trigger, the single output of which is connected to the first input of the third its element AND and through the second element NOT with the start input of the first signature analyzers of the group, the output of the clock generator is connected to the second input (of the third element AND of the control unit! and with the second input of the element AND block • of a custom delay, the output of the third element AND block the control is connected to the counting input of the second counter, with the census permission input to the (n + 1) -th signature analyzer of the group, with the first input of the OR element. of the custom delay unit, the outputs of the third switch of the control unit are connected respectively about with single and zero inputs of the fifth trigger of the control unit, the single output of which is connected to the write enable register of the custom delay unit, the information outputs of which are connected to the counter information inputs, the output of the AND element of the custom delay unit is connected to the counter input, the overflow output of which connected to the second input ^ of the OR element of the custom delay unit, with the input of the first OR element of the control unit and with the input of the initial installation of the third trigger of the control unit Ia, the output of OR adjustable delay block is connected to a clock input of the first η signature analyzer, the control unit outputs a group of switches are connected to the data inputs of the adjustable delay unit register.