SU1068931A2 - Device for comparing binary digits - Google Patents

Abstract

DEVICE FOR COMPARISON OF BINARY NUMBERS on author. Ev. No. 822178, characterized in that, in order to increase the reliability of the comparison result, the device contains an additional delay element and a trigger, wherein the device control input is connected via an additional delay element to a single additional trigger input, the zero input of which is connected to the device reset input, and right my - with the third inputs of the second and elements I. (L

Description

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The invention relates to automation and computing technology and can be used in the implementation of discrete automation hardware. .

According to the main author. St. No. € 22178, a device for binary numbers is known, comprising a p-bit counter, the setup inputs of which are connected to the tires of the first comparative device number, trifi bi, AND and OR elements, delay element, and the p-counter counter overflow output connected to the single input of the first trigger, the direct output of which is connected to the first inputs of the first and second elements I, the output of the first element I connected to the single input of the second trigger, zero inputs of the first and second trigger connected to device reset, the inverse output of the first trigger is connected to the first input of the third element And, the second input of which is connected to the inverse output of the second trigger and the second input of the second element And, the outputs of the second and third elements And are respectively the first and second output 1 "and devices my output of the second trigger is the third output of the device, the first input of the OR element is connected to the input input of the second number of the device, the second input is connected to the control input of the device,

and the output of the OR element is with the counting input of the counter and the second input of the first element AND {1J.

The disadvantage of this device is that the reliability of the comparison result is low, since after the reset signal passes, even before the latch signal is received by the control of the latching signal, a single signal is set on the output bus, which can be mistakenly taken as the result of the comparison. In addition, if, from the moment the number B arrives at the device input and until the fixation signal arrives at the control input of the device, the output bus 14 (A B) with a single signal, which can also be taken as comparison result.

The aim of the invention is to increase the reliability of the binary number comparison result.

The goal is achieved in that the device for comparing binary numbers contains an additional delay element and a trigger, wherein the device control input is connected via an additional delay element to the single input of an additional trigger, the zero input of which is connected to the device reset input and the direct output to the third inputs second and third elements I.. The drawing shows the functional diagram of the device.

The device will hold the p-bit counter I, bus 2 of the first compared NUMBER, input 3 of the input in the second comparable number, input 4 of the device control, input 5 reset, the element OR 6, the element 7 for the holders, triggers 8 and 9, the elements AND 10-12, output tires 13-15, trigger 16 and delay element 17,

 The device works as follows.

Before starting the comparison, input 5 receives a reset signal, which sets triggers 8, 9, and 16 to the zero state. A zero signal at the direct output of trigger 16 prohibits the appearance of outputs.

5 elements of both 11 and -12 single signals, and on all outputs of the device 13-15 there will be zero values of the signals. The first comparison number is fed over the bus in such a way that its inverse value is set in the n-bit counter. After that, the input 3 through the element OR 6 to the information input of the least significant bit of the counter receives the second number in the form of a number-pulse sequence. When the second number is transmitted, at the entrance

5 4 controls receive a signal and after some time a comparison result is formed in one of the output buses 13-15 as a single signal. This time is determined by the magnitude of the delay, the element 17, the switching delay of the trigger 16

O and elements 11 and 12 for outputs 14 and 15 and the switching delay of trigger 9 and element 10 for output 13; At the exits

13-15, the comparison result is maintained until the reset signal on input 5 arrives.

Let A B 101, then in the counter I the number A is set in the form of an inverse code 010. After being received at the counting input

. the lower bit of the pulse number of 101 pulses in the counter 1 is summed 010-L 101 111. After the signal arrives at input 4 of the control signal, one more is added to the counter 1, and an overflow signal is detected at the high-bit output, which after a delay of element 7 sets to one state the trigger 8 immediately after the termination of the signal at the output of the element OR 6. The single state of the trigger 8 and the zero state of the element

0 And P at output 14 (A B) with zero signals at outputs 13 and 15..

Let, for definiteness and. After receiving the "Iola" in the counter 1, the inverse value 010 is set, and after receiving the counting input, the IM 5 pulses the trigger 8 is set to one. After receiving 4 fixation signals at the output of the AND 10 element, a single signal is generated and the tprtrrep 9 is set to one cog 1f is taken, thus the definite unit cHir output13 () and are on highs 14 and 15. Suppose for definiteness that B 100. After receiving the number in counter 1, the inverse value of 010 is set, and after receiving the counting input 100 pulses are received the amount of OJO + 100 110. After imbalances on input 4 of the signal (the Lucchein sumM is increased by the admin: MO + 001 -P1. Since the overflow signal g does not appear in this case, the triggers 8 and 9 remain at zero. The trigger 16 is set to one state a latching signal, prupayuschim on input 4 of the control, while the output 15 () with the help of eleknty And 12 forms a single signal at zero signals at outputs 13 and 14. The delay element 7 in the device can oTcytCtfioBaTb in general, if There is a necessary pregnant relationship. ,,; . . -. :: - Thus, the introduction in the device of the second delay element and the third-three gager with appropriate connections allows to significantly increase the quality of the binary-binary comparison result, P) 6d, since the unit comparison signal is right on one of the output devices only after arriving at input Jn of its latch signal,

Claims (1)

DEVICE FOR compare _Mr. Nia binary numbers of the authors. St. No. 822178, characterized in that, in order to increase the reliability of the comparison result, the device contains an additional delay element and a trigger, the control input of the device through an additional delay element connected to a single input of an additional trigger, the zero input of which is connected to the reset input of the device, and a direct wave - with the third inputs of the second and third elements I.