SU1050122A1 - Device for checking counter code - Google Patents

Description

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The invention relates to a pulse technique and can be used to check the location of the code accumulated by the counter of pulses in the permissible measurement zone, which is used in the construction of various instrumentation, such as automatic flaw detectors.

A device containing a counter, a descrambler, elements NOT, beyond the limit sensor is known}.

The disadvantages of the known device is that, although the device has an adjustable lower limit of comparison, it has limited functionality because it does not allow to establish a control zone bounded on both sides. Moreover, the device has an unreliable estimate of the amount accumulated. pulses. If the switch is set, for example, to a number (in the decimal system), and a number in the counter, then with a counter conversion factor of 10, the number and pulses U,, 33, etc. on output, it will give the same amount as the number of pulses 3, if the given limit is 5, d is many times surpassed

A device for controlling the counter code is known, containing an input bus, a reset bus, a polling bus, an OR element, an IS-NOT element of a decoder block and n counting blocks connected in series, each of which contains a counting decade, and containing 10 RS flip-flops and 10 additional AND elements -NO, the outputs of the counting decades are connected to the corresponding inputs of the decoder unit, the first output of which is connected to the clock input of the first trigger, the remaining outputs of the decoder unit are connected respectively to the first inputs of the additional elements Combus NAND, whose outputs are connected respectively to the clock inputs of the remaining triggers, the inverse outputs of all the triggers are connected to the inputs of the OR element, the output of which is connected to the first input of the NAND element, the second input of which is connected to the interrogation bus, the direct output of each trigger connected to the second input of the corresponding additional element, the installation inputs to zero of the flip-flops are connected to the installation inputs to zero of the counting decades and to the bus

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reset, the input bus is connected to the counting input of the counting decade of the first counting unit 2 J,

The disadvantages of the known device are the lack of control capability in the range of codes limited by the upper and lower limits, the absence of the possibility of changing these boundaries during operation and the relatively large complexity of the device, which ultimately leads to a decrease in hope.

The aim of the invention is to increase the credibility.

In order to achieve a post-objective goal in the device 1, an ontrol counter code containing an input bus., A reset bus, a polling bus, an NAND element and n counting blocks connected in series, each of which contains a counting decade, a decoder, two OI-flip-flops, all the counting blocks, except for the last one, contain two additional elements, in each estimated block, the ai steps of the counting decade are connected to the inputs of the decoder, the installation input to the zero counting decade is connected to the installation inputs to zero of the RS flip-flops and connected to the reset bus, the input bus is connected and with the clock input of the counting decade of the first counting unit, the interrogation bus is connected to the first input of the NAND element, two decimal switches are entered into each counting block, and the first and ator elements NOT whose inputs are connected are entered into each counting block except the last one respectively, with the movable contacts of the first and second dec tentative switches J, the outputs of the first and second elements are NOT connected respectively to the first inputs of the first and second additional AND AND elements whose outputs are connected respectively with the inputs of the first and second RS-flip-flops, the second inputs of the first and second I-NC additional elements are connected respectively to the direct outputs of the first and second RS-flip-flops of the subsequent counting block, in each counting block the switches are connected to the corresponding outputs of the decoder; in the last counting block, the movable contacts of the descriptive switches are connected to the inputs of the unit e, the unit 31 of the corresponding RS-flip-flops, sec The first and third inputs of the NAND element are connected respectively to the direct output of the first and inverse outputs of the second RS flip-flops of the first counting unit. The drawing shows a diagram of the device control code two-decade counter. The scheme contains counting decades 1 and 2; input bus 3, decoders k and 5 dess position switches 6-9, elements NOT 10 and 11, elements AND-NOT 12 and 13, triggers, element AND-NOT 18, polling bus 19, output bus 20, reset bus 21. The input bus 3 is connected to the clock input of the counting decade 1, the output of the last bit, which is connected to the clock input of the counting decade 2, the outputs of the counting decade 1 are connected to the inputs of the decoder 4, the outputs of the counting decade 2 are connected to the inputs of the decryptor 5, the outputs of which are connected with fixed contacts of the same name of switches 8 and 9, the movable contacts of which are connected respectively to the installation inputs to the unit three Gerov 16 and 17, the forward outputs of which are connected respectively to the first inputs of the elements AND-NOT 12 and 13, the second inputs of the cat The cells are connected respectively to the outputs of the elements HE 10 and 11, the inputs of which are connected respectively to the movable contacts of the switches 6 and 7, the He-movable contacts of the same name are connected - to the corresponding outputs of the decoder, the outputs of the elements AND-NOT 12 and 1 are connected respectively to the inputs of the installation into the unit of triggers The I and IS inputs of the zero setting are connected to the installation inputs of zero counting decades 1 and 2, flip-flops 1b and 17 and connected to the reset bus 21, the inputs and output of element 18 AND-NOT are connected respectively to the direct output t At | - hera 14, with inverse trigger output 15, with interrogation bus 19 and with output bus 20. The device operates as follows. On command. The reset all counting decades 1 and 2 and the ft-17 triggers are set to the initial (zero) state. The input bus 3 receives pulses. During the accumulation of pulses, the codes of decade 1 and 2 and the decoder t and 5, respectively, change in all bits. When passing the specified comparison limits in the lower order, the logical contacts of the switches 6 and 7 periodically receive logical O signals. At the outputs of the inverters, logical 1 signals appear, which are fed to the first inputs of the AND-NOT elements T2 and 13. But the triggers 1 and 15 in the low-order do not change their state (do not transfer to 1), since logical inputs O and (prohibition) from the flip-flops 16 and 17 of the subsequent high-order bits are applied to the second inputs of the AND-HE elements 12 and 13. If the number of pulses exceeds the lower limit of the highest decade, then the logical O signal from the decoder 5, directly through the contacts of the switch 8, flips the trigger 1b of the oldest bit to state 1. This signal will allow the decoder pulse to pass through the NAND element of the previous digit Yes, and so on, until it is transferred to 1 trigger 14 to memorize the transition of the lower limit to the 3 lowest decade. This serves as a signal of the moment when the number of accumulated pulses passes through the lower limit of the control. Similarly, when the upper set limit is passed, the trigger 17 in the senior counting block first changes the state, allowing the pulses to pass through the AND-NES element of the previous counting block, etc., until it triggers 15 triggering the upper limit in the lower counting block. This serves as a signal of the moment of transition of the number of accumulated pulses through the upper limit of comparison about 8, the table shows three possible combinations of signals at the inputs of the circuit of the AND-HE element 18 after the arrival of the enable signal 1 via the interrogation bus 19, as well as the signals on the bus 20 of the device

N is the lower limit of comparison; Nn - the upper limit

compare.

From the table it can be seen that after the arrival of the interrogation signal, the signal on the bus 20 of the device is equal to the logical O only in the case when the number of accumulated pulses falls within the predetermined limits of comparison.

Then, on bus 21, all counters and triggers are reset, and the device is ready for the next monitoring cycle.

Using the proposed device will allow operations to compare the numbers recorded in the counters with the numbers corresponding to the lower and upper limits of the comparison and easily reprogram the control zones without using a computer, as well as s (to increase reliability compared to the known device. Nitty limit 6

Claims (1)

COUNTER CODE CONTROL DEVICE containing an input bus, a reset bus, a polling bus, an NAND element and η counting blocks connected in series, each of which contains a counting decade, a decoder, two RS-flip-flops, all counting blocks except the last one contain two additional AND-NOT elements, in each counting unit the outputs of the counting decade are connected to the inputs of the decoder, the input of the installation to zero of the counting decade. is connected to the inputs of the installation to zero RS-flip-flops and is connected to the reset bus, the input bus is connected to the clock input of the counting decade of the first counting unit, the polling bus is connected to the first input of the element-AND-NOT, about t, and which, in order to increase reliability, in each two ten-position switches are inserted into the counting unit, and in each counting block, in addition to the last, the first and second elements of HE are entered, inputs, which are connected respectively to the movable contacts of the first and second ten-position switches, the outputs of the first and second elements are NOT connected to accordingly, with the first inputs of the first and second additional AND-NOT elements, the outputs of which are connected respectively to the installation inputs to the unit of the first and second RS-flip-flops, the second inputs g of the first and second additional AND-NOT elements are connected respectively with the direct outputs of the first and second RS-triggers of the subsequent counting unit, c. in each counting unit, the same fixed contacts of the ten-position switches are connected to the corresponding outputs of the decoders, in the last counting block, the movable contacts of the ten-position switches are connected to the installation inputs to the unit of the corresponding RS-triggers, the second and third inputs of the AND gate are connected respectively to the direct output of the first and inverse ¹ output of the second RS-flip-flops of the first counting unit. SU. „, 1050122> ΐ 105