SU1049876A1 - Stabilized secondary supply source - Google Patents

Abstract

A STABILIZED SECONDARY ELECTRICAL POWER SUPPLY, containing converter cells connected in series in an output, a reversible counter, the outputs of which are connected to the control inputs of the converter cells, a pulse-width modulator, the output of which is connected to the control input of the converter cell inverter, and a modulating input output. In conclusion, the first element And, the first and second voltage comparators and the source of the reference voltage, characterized in that, in order to increase efficiency and speed, It has the second and third elements And, the divider of the voltage source, and the converter cells are made with a common transistor inverter with a current sensor at the input, the first inputs of the comparators are connected to the output terminal, the second input of the first comparator is from the upper arm of the divider of the reference source voltage, and the second input of the second comparator - with the output of the lower arm of the divider of the source of the reference voltage, non-inverting output of the first, the comparator through the second element I is connected to the thickness “-1 reverse A second counter, inverting the output of the second comparator through the third element I - with the bus “+ 1 reversible counter, the second inputs of the second and trading elements AND SS are connected to the input of clock pulses, the third input of the third element I - with the current sensor stroke, the inverting input the first and non-inverting output of the second comparators - with the corresponding inputs of the first two-input element And, the output of which is connected to the input of the inclusion of the pulse-width modulator. 4 from 00 about:

Description

The invention relates to electrical engineering and can be used in the development of secondary power supply equipment for electronic equipment.

A device is known which contains a push-pull transistor inverter with a current sensor and an isolation transformer having N secondary windings, N rectifying bridges, each of which is connected to the terminals of the respective secondary windings of the transformer, N controllable keys, each of which is connected to one of the terminals of the corresponding rectifier of the bridge, N decoupling diodes, connected in the opposite direction between the corresponding control key and the other output of the rectifier bridge, all of which the diodes are connected to each other in series and in parallel with them; a l-shaped filter is connected, as well as a distributor of key control pulses 1.

However, in this device, efficiency is reduced when switching the steps of a push-pull transistor inverter, since the transistor leaves the saturation region to the active region for the time required to recharge the output filter capacitor.

In addition, the speed is limited by the capacity of the filter and the internal resistance of the current inverter, which, when switching stages, operates in the mode of the current source, -. ripple level and stability are limited by the discreteness of the electronic switch-circuit.

The closest in technical essence to the present invention is a stabilized DC / DC converter containing converter cells connected in series in an output, a reversible counter, the outputs of which are connected to the control inputs of the converter cells, and a lattice-pulse modulator whose output is connected to the input of the inverter converting. cells, and a modulating input with an output terminal, an AND element included in the control circuit of a reversible counter, the first and second voltage comparators, and a source of reference voltage.

At the same time, between the output of the pulse-width modulator and the power supply circuit of the transistor inverter of the converter cell, a key voltage regulator is turned on, and to control a reversible counter, feedback loops are used that connect the inputs of the reversible counter through the comparators to the converter output and key voltage regulator 2

The disadvantages of the known device are low efficiency and speed, which are caused by the presence of a key regulator in the power circuit of the converter cell and the fact that cell switching takes place depending on the voltage on the key regulator.

The purpose of the invention is to increase efficiency and speed.

This goal is achieved in that the device containing the converter cells connected in output in series is a reversible counter, the outputs of which are connected to the control inputs of the converter cells, a pulse-width modulator whose output is connected to the Control Output of the converter cell inverter, and the modulating input is with

5 output terminal, the first element And, the first and second voltage comparators and the source of the reference voltage, introduced the second and third elements And, the divider of the source of the voltage, and the converter cells are made with a common transistor integrator with a current sensor at the input the first inputs of the comparators are The second input of the first comparator is connected to the output of the upper arm of the divider of the reference voltage source, and the second input of the second comparator is connected to the output of the lower shoulder of the divider of the reference voltage source, the non-inverting output of the first com- parator through the second element I is connected to a thickness "-1 reversible counter, inverting the output of the second comparator through the third element And connected to the bus" + 1 reversible counter, the second inputs of the second and third elements And connected to the input of clock pulses, mp Tille input of the third AND gate with the output current sensor, a first inverting output and noninverting output of the second comparator connected to corresponding inputs of said first two-input AND gate whose output is connected to the input incorporation schi0 Rotne-width modulator.

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FIG. 1 shows a block diagram of the device; in fig. 2 - stress diagrams at characteristic points of the circuit.

The stabilized constant-voltage converter consists of a push-pull transistor inverter 1, controlled rectifying stages 2, a smoothing L-shaped filter consisting of droplets 3 and a capacitor 4, comparators 5 and 6, logic elements And 7-9, a reversible counter 10, a pulse-width modulator 11, a voltage divider, made on resistors 12 and 13, power inputs 14 and 15, and output pins 16 and 17.

5 A push-pull transistor inverter 1 consists of switching transistors 18 and 19, a master oscillator 20, an isolation transformer 21 comprising a wound winding 22 and a series of secondary loops 23, and a current sensor 24. The controlled rectifying stage 2 consists of a rectifying bridge with diodes 25-28, transistor switch 29 and isolation diode 30.. Each of comparators 5 and 6 consists of an operational amplifier 31 and an inverter 32. Reversible counter 10 operates in binary code and contains a decoder (not shown, which directly controls transistor switches 29. The device operates as follows. In the initial state on the output pins 16 and 17, the voltage is absent, while the reversible counter 10 is set to its original zero state, in which its outputs do not have signals, and therefore the transistor switches 29 of the rectifying stages are When the voltage is applied to the inputs 14 and 15. The power supply: the master oscillator 20, which produces an alternating square voltage alternating voltage, starts operating. This voltage goes to the bases of the switching transistors 18 and 19 When the clock pulses are fed to the input busbar G of logic elements AND 8 and 9, a signal of a logical unit appears at the output of logic element AND 9, and there is no signal at the output of logic element AND 8. This is due to the fact that at the other inputs of these logic elements, the signals coming from the outputs of the corresponding comparators 6 and 5 are in antiphase. In addition, the signal at the output of the current sensor 24 in the absence of current in the load circuit has a logic level. 6 When the first pulse arrives at the “+ 1 reversing counter 10 input, it starts counting the pulses in binary code in the direction of direct counting. The state algorithm on the output of the reversible counter is given in the state table. As a result of the arrival of a counting pulse at the “+ 1” input, one of its outputs (for example, a) produces a voltage drop, which turns on the transistor switch 29 of one of the rectifying stages 2. In this case, the output AC voltage of the push-pull transistor inverter is fed to the input G 3 and 4 filter. This voltage provides the oscillating or aperiodic charge of the capacitor (depending on the nature of the characteristic resistance of the LC circuit of the L-shaped filter 3 and 4, taking into account the effect of the load). The charging current of droplets 3 and capacitor 4, taking into account the current in the load circuit, causes a current in the sensor circuit, 24 currents. As a result of the flow of charging current of the LC circuit, a logic zero signal is generated at the output of the current sensor, which blocks the arrival of clock pulses at the input -f 1 of the reversible counter 10 by means of the AND 9 logic element for the charging time of the capacitor 4 to the set value. After the blocking signal on charging current of the LC circuit is removed, the next pulse appearing at the output of the logic element AND 9 appears at the input of the “+ 1 reversible counter 10. In this case, the reversing counter 10 changes to another state associated with on the other output (b) of the logic unit, which turns on the second transistor switch 29. At the first output (a) of the reversible counter 10, zero is set, so the first transistor switch is turned off. As a result of the next voltage jump at the input of the filter, the capacitor is recharged by the same amount. At the time of charging capacitor 4, the output signal of current sensor 24 blocks the arrival of clock pulses on. the input "+ 1 reversible counter 10 in the same way using an AND 19 gate. Then the processes in the circuit are repeated and the transistor switches are turned on according to the algorithm specified in the table of states. With each switching of the transformer windings, the voltage in the steady state increases by a constant value. The switching process of the output windings 23 using transistor switches 29 occurs until the voltage at the output of the device reaches the lower value of the reference voltage UOHK ... This triggers the comparator 6.J (Fig. 26). As a result of the operation of the comparator 6, the input of the +1 reversible counter is blocked using an AND 9 logic element. and in the counter the counting of pulses in the forward direction is stopped. Since the signal c2 of the comparators outputs is fed to the input of the AND 7 logic element, taking into account the states of the comparators (Fig. 2.6 and c), the output of the AND 7 logic element produces a logical signal (Fig. 2, d), which includes the latitude pulse modulator 11. When the pulse-width modulator And is turned on, the master oscillator starts operating in the modulation mode of alternating voltage by duration. The depth of modulation of the alternating voltage pulses 3 is determined by the feedback signal on the output voltage supplied to the second input of the pulmonary modulator 11 vCa. In this mode, the device operates like a normal key regulator, in which voltage is stabilized by pulse widths. In case the output voltage of the device exceeds the value of the specified voltage Uojepx. . (Fig. 2, a), another comparator 5 is triggered (Fig. 2.0). When the comparator 5 is triggered, the pulse-width modulator, 11 turns off using the AND 7 match element (Fig. 2, and the input "-1 of the reversing counter 10 is turned on, since the logical signal" 1, coming from the output of the comparator 5. In this case, the next pulse coming to the clock pulse bar shifts the reversing counter in the opposite direction, and the output voltage of the device decreases discretely by a predetermined amount. The output voltage decreases due to the load current until the device enters the zone of pulmonary regulation (Fig. 2, a). Further, the processes in the scheme are repeated, For greater clarity in Fig. 2, voltage plots on the clock pulse strip are shown, in Fig. 2 , e - the pulses at the input "+ 1 and in Fig. 2, g - the pulses at the input" -1 of the reversing counter 10 for the case of direct and reverse counting. By selecting the number of controlled rectifying stages, the output voltage can be discretely adjusted with a given accuracy and significantly increase the degree of stabilization due to the pulse-pulse About regulation. Due to the fact that the depth of the pulsating pulse control is usually a fraction of a percent, the proposed DC / DC converter has several advantages that are absent in known devices, namely: - a predetermined level of pulsations is provided by using a filter with an insignificant value reactive elements; - the device has a high speed in the conditions of work on dynamic load; - the device can operate with the characteristics specified above in the wide range of input and output voltages, since the voltage form does not change. ) i LG Exit

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Claims (1)

A STABILIZED SECONDARY POWER SUPPLY SOURCE, comprising converter cells connected in series output, a reverse counter, the outputs of which are connected to the control inputs of the converter cells, a pulse-width modulator, the output of which is connected to the control input of the inverter of the converter cell, and the modulating input is connected to the output terminal, the first element And, the first and second voltage comparators and the reference voltage source, characterized in that, in order to increase efficiency and speed, into it the second and third elements And, the divider of the reference voltage source, and the conversion cells are made with a common transistor inverter with a current sensor at the input, the first inputs of the comparators are connected to the output terminal, the second input of the first comparator is connected to the output of the upper arm of the divider of the reference voltage source, and the second input of the second comparator - with the output of the lower arm of the divider of the reference voltage source, the non-inverting output of the first, the comparator through the second element And is connected to the bus "-1" reverse sensor, inverting the output of the second comparator through the third element And - with the bus "+ 1" reverse counter, the second inputs of the second and third elements And g are connected to the input of clock pulses, the third input of the third element And - with the output of the current sensor, inverting the input of the first and non-inverting the output of the second comparators - with the corresponding inputs of the first two-input element And, the output of which is connected to the input of the inclusion of a pulse-width modulator. SU ... 1049876>