SU1034042A1 - Microprogram checking device - Google Patents

Abstract

. DEVICE FOR COUNT01. ; FIRMWARE,. containing the first-., memory block, perHCTJp microinstructions,. the first and; SECOND Triggers.result, the control trigger, the first, second, third and fourth elements AND, the first and second elements EFI, the delay element and the block elements AND, with the "OUTPUT of the first element AND connected to / / with the INPUT of the read the first memory block, the OUTPUT of which is connected .. to the INPUT of the microinstruction register, output-: the microoperations floor and the microcommand address register floor are connected to the inputs of the first element OR, the output of the first delay element and well: the left OUTPUT of the control trigger. Dineny, respectively, and the first. the second inputs, the second element And, the unit outputs of the first and second result triggers are connected to the first inputs of the third and fourth elements And the corresponding zero outputs of the first and the second trigger inputs of the result triggers are connected to the second inputs of the fourth element and the fp & which are connected to the first and second inputs of the second element | OR, respectively, from whether it is so that, in order to improve the reliability of the control, it has a trigger trigger, a one-shot, -; , counter, second and third memory blocks, switch, fifth; sixth and seventh .-:: my -elements: And, the second and third .. -:.; .delay elements, and the input is sync: device ropings and unit 11CHN1 1st. V. , The trigger start EXIT is connected accordingly with. first and second entry:; dami; In addition, the exit of which is connected with the first entrances; . And the second and sixth elements And through. the first one is the second ;, element C) delay v. e6 counting input (uh counter, gshkod-; overflow of the counter is connected to. .countable input 6ds l trigger control / -. information outputs of the counter connect. yeny with addressed inputs; the second blr-S k palct, first informadaonnymi: .- .inputs: .x1mutator and the first: inputs: -: f / 1 |: g -, mi block of the element: in AND ;.the outputs of which are V ,. are connected by information inputs f / m nepspEo of the memory block, single - : control trigger output. Soy, E jench- g.: With the first control input,. of the torus .. with the second input of the sixth; elements that AND AND, which is connected to the input Dami Read the second and third / -: memory blocks and with the inputs of the syncryr-tion of the Triggers of the result and through .., -: - the third element of the support with the third; the inputs of the third and fourth e; the elements And, zero OUTPUT of the trigger of the right : Jaeni is connected to the second, inputs of the block of elements and, the second input of the first element, the second element, the second control unit, the gateway; the switch, and one-way; RtoE1., With the input signal of the second element OR the output address field of the register -Y (Okomand is connected to the second .informational input of the switch, EBT code KoTogfoFo with address input of the Ftrego memory block, you-. second move; element I is connected to the first input of the seventh element and not; the recording inputs of the second and third memory blocks, whose outputs are soy; dknen respectively with the D inputs

Description

the first and second triggers of the result, the output of the first element OR is connected to the information input of the second memory block and the second input of the seventh AND element, the output of which is connected1 | with the information input of the third memory block, the output of the second element

OR is connected to the start trigger zero input, the single input of which is the device start input, the outputs of the third and fourth I elements are the first and second error outputs of the device, respectively.

The invention relates to digital computing and can be used in the development of hardware devices for the control software of the liver. A device for controlling firmware is known, which contains a controlled firmware automaton, an AND, OR, a trigger, a delay element 1. The disadvantage of this device is the low completeness of the control, caused by the lack of means of controlling subjective errors. . A device for monitoring the execution of programs is known, which contains triggers, AND, OR, delay elements, C3 memory unit. The disadvantage of this device is the large amount of con-thro means; l, due to the fact that the device must store information about all the allowed sequences of modules of the program. Closest to the proposed by. the technical essence and the achieved positive effect is a device containing a microprogram memory block, microinstructions register, result register, control trigger, first, second, third and fourth elements AND, first and second elements OR, delay element and block elements AND, the first element I is connected to the input of the readout of the microprogram memory unit whose output is connected to the input of the register of microinstructions, the outputs of the field of microoperations and the address field of the register of microinstructions are connected to the input of the same; The first element OR, the output of the first delay element and the zero output of the control trigger are connected respectively to the first and second inputs of the second element, the unit outputs f of the first and the second result trigger are connected to the first inputs of the third and fourth elements, respectively, the zero outputs of the first and the second trigger of the result register is connected to the second inputs of the fourth and third elements AND, respectively, the outputs of which are connected to the first and second inputs of the second element OR respectively 3. Disadvantage th device is a narrow field of application due to the low control completeness, subjective errors ,. in the specified device, monitoring of the errors is a deadlock type, i.e. errors made at the design stage and which lead to the fact that there are micro-comans (commands) in the microprogram (program) that have no followers. Thus, the fullness is low. The control is due to a limited class of detectable errors. In addition, this device is focused on the use in the mode of the main operation of the monitored firmware of the automaton, i.e. in the operating control mode, which reduces the reliability of the control machine. The purpose of the invention is to increase the reliability of the control. The goal is achieved by the fact that in a device for controlling microprograms:, - containing the first memory block, register, microcommands, first and second result triggers, control trigger, first, second, third and fourth elements AND, first and second elements OR, element delays and a block of elements And, with the output of the first element And connected I.. . -. , with the read input, the first firmware memory block, the output of which is connected to the register of microinstructions, the outputs of the microoperations field and the address field of the mic: rokomando are connected to the inputs of the first OR element, the output of the first element of the control and the zero output of the control trigger are respectively connected to the first and the second inputs of the second element And, the unit outputs of the first and second result triggers are connected to the first inputs of the third and fourth elements And, respectively, zero outputs of the first and second trigger the result is connected to the second inputs of the fourth and third elements AND, respectively, whose outputs are connected to the first and second inputs of the second OR element, respectively. A trigger, start, one-shot, counter, second and third memory blocks, switch, fifth, sixth and the seventh And elements, the second and third delay elements, and the clock input of the device and the single trigger trigger output are connected respectively to the first and second inputs of the fifth And element, the output of which is connected to the first inputs of the first and six About the I elements and through the first and second delay elements with the counter input of the counter, the output of the overflow of the counter is connected to the counter input of the control trigger, the information outputs of the counter are connected to the address inputs of the second memory block, the first information inputs of the switch unit And the outputs which is connected to the information inputs of the first memory block, a single output, a control trigger is connected to the first control input of the switch and the second. the input of the sixth element AND, the output of which is connected to the inputs of the second and third memory blocks, with the synchronization inputs of the result triggers and through the third delay element with the third inputs of the third and fourth AND elements, the zero output of the control trigger is connected to the second inputs of the AND element block , the second input of the first Element And, the second control input of the switch, and through the one-shot one with the second input of the second element OR, the output of the microcommand address field is connected to the second information input mmutator, the output of which is connected to the address input of the third memory block, the output of the second element I is connected to the first input of the seventh element I and to the recording inputs of the second and third memory blocks, the outputs of which are connected respectively to the D inputs of the first and second triggers result, the output of the first element OR is connected to the information input of the second memory block and the second input of the seventh element AND, the output of which is connected to the information input of the third block n: amti, the output of the second element OR is connected to the zero input trigger The start-up, the single input of which is the start input of the device, the outputs of the third and fourth elements of AND are the corresponding first and second outputs of the error of the device. Each word (ruler) $, stored in the memory block, is assigned a two-bit flag 7 (R, -, PI), and (O, if there is no information in the ruler S, 1, if there is a nonzero information in the ruler 5y. 1, if the address of the memory block is written, the address of the ruler Sf; O, otherwise., M is the number of rulers in the memory. Then i has the following expression 00, if the ruler is not used in firmware, for recording microcommands; 10, if a microcommand is written in the ruler but is unreachable. (C) t; 03. if there is a dead end microcoma in the ruler The NDA, whose address part is the address of the ruler 5, 11, if in the S. ruler, is a microinstruction that is not: C unreachable and is not the end microcommand of the stub section. Signs are formed by sequentially reading information from memory block and analysis of address parts. If, 10, then this indicates incorrectness of the microprogram, i.e. and there are errors in it, such as deadlock or unreachable, a vertex. Combinations f; C (O 0.11 are sparse. Introduction to the device of the counter and the connections due to it allows to generate addresses of the memory block lines, and when entering the last line to form an operation control signal. The introduction of the switch and the connections resulting from it to manage the address chains of the third memory block. -. The introduction of the second and third blocks of the message and the conditioned links is necessary for the storage of the signs P and R | g. The introduction of the trigger trigger, the fifth AND element and the conditioned ones, allows them to control innings sync pulses into the device. Introducing the sixth element AND, and the connections caused by it, it is necessary to control the delivery of the read pulses to the second and third blocks, memory ..., ... .The introduction of the seventh AND element and the connections resulting from it allows you to control the recording sign V, into the third memory block. Introduction of the one-shot and associated connections. It allows to form a stop signal of the device after testing is completed. Connection of the outputs of the third and fourth elements And with the outputs of the device's error, and the output of the second IL element And with a zero input of the start trigger, it allows generating error signals and blocking the operation of the device when left. The introduction of the second delay element and the relations due to it is necessary for the delay of the pulse during the recording of information in the second and third memory blocks. The introduction of the third delay element and the relations due to it allows delaying the polling pulse. Triggers the result by the read time. Information from the second and third memory blocks. A: The drawing shows a functional diagram of a device for controlling firmware. . . The device contains a trigger-. 1. start. qa, fifth element i 2, .first 3 and. et ry 4 delay elements, counter 5,; block b of elements i, first element i 7, first block 8 of the memory of the microcoma; nd-register 9 microinstructions with Paul 1 and .addressny, 9.1 and microoperations .§., 2, appealing. controlled machine. . .itO-, first element-OR 11, three-goer 12 controls, switch 13, second element-I 14, seventh element 15, third, memory block 16, first: result trigger 17 and second .trigger. 18 results, the third .19 and even; ve: ou 1 20, the elements And, the second 21 and the sixth 22 elements And, the third block 23 nateti., - the third element 4. Zad.rzh-ki and one vibrato.r 25. Except Tggo, symbols 26-29 designate the start input and the sync pulse, respectively: the first and second outputs of the device error. . ; In block 8 of the memory, information is stored on the firmware (programs) which is read into register 9. Counter 5 performs form-out of the address when reading information from blocks 8.16 and 23 of memory. The trigger 12 controls the mode of operation of the device, and the trigger 1 controls its triggering and stopping. Memory blocks 16 and 23 are designed to store the P signs. Triggers 17 and 18 remember them after reading from memory blocks-16 and 23. Items 22,14 and 15 control the writing and reading of information from these blocks. The address switch 13, depending on the operation mode, switches the address circuits of the memory block 16. ., Element OR 11 fixes a non-zero code recorded in register 9. Elements AND 19 and 20 generate error signals based on the code in triggers 17 and 18, Element OR-21 triggers a trigger signal 1 when an error signal appears or the operation ends. The proposed device operates in two modes: the mode of formation of signs to the mode of analysis of signs, A /. The TL-I mode of formation of the signs of the initial state, all the triggers and the counter are reset, in blocks 16 and 23 of the memory are recorded well; left, information. In block 8 of the memory, monitored firmware (programs) are recorded. In the address field of the latest microinstructions, the starting addresses of the corresponding microprograms are recorded. After arriving at the output: 26 of the signal. The trigger 1 is set to one state and the first pulse from the device input 27 passes to the output of the element 2. This reads the information stored in the zero (initial) line of the memory block 8 . With a delay equal to the time of reading information from block 8., a pulse appears at the output of element 3 and permits the recording of information in blocks 16 and 23. The address in block 16 is fed from the output of field 9.2 through switch 13, and in block 23 directly from the output of the counter 13. If a non-zero code is written at the starting address in block 8, then in blocks 16 and 23 a unit will be written to the corresponding addresses, otherwise —.nul .: After recording the information in blocks 16 and 23 impulses: from the exhaust signal element 4 delay increases aet- .. by one the contents of the counter 5, .forming it the address with eduyuschey line. With the arrival of the next sync on the entrance. 27 cycles of operation are repeated as described: algorithm. With the appearance of an overflow signal at the output of the 5-signal counter, trigger 12 is set to a single point and the device switches to the second mode. Feature analysis mode 7f /. The initial state of the device before starting the operation in this mode is as follows :; the triggers 1 to 12 are in the single state, the counter 5 and the triggers 17 and 18 are cleared. Signs are recorded in the memory blocks 16 and 23. . On the first impulse, passing through the elements AND 2 and OR. 22, information is being read from blocks 16 and 23 on the triggers 17 and 18. Address

the cells from which information is read from both blocks is determined by the code in counter 5. Since the zero code is written in it, the sign Kf is read from blocks 16 and 23, then, in accordance with expression (4), it is decrypted: if. OOVll, the signals gated by the signal 1 output delayed by the time the information is read. 24 delays, at the outputs of the elements And 19 and And 20 are absent, and the passage of the next clock pulse is broken; if 1fc 01V10, then a signal appears at the output 28 or 29, which passes through the OR element 21 to reset the trigger trigger, informing at the same time about the type of error.

At 12 OOV11, the next pulse reads from blocks 16 and 23 of the IZ attribute, the analysis of which

performed in the same way as the algorithm described above.

If, after reading the last symptom T), an error is not detected, then by the overflow signal of the counter 5, the trigger 12 is set to the zero state, and the one-shot 25 produces a zero pulse of the trigger 1 of the start.

In a manner that, the technical advantages of the proposed device in comparison with the prototype and the basic object are in higher control completeness (by a factor of 2-3) and lower programs and firmware due to insertion and removal of unrealizable areas.

The use of the invention allows to reduce development time / increase reliability and QTb bb software.

Claims (1)

DEVICE FOR CONTROL. MICROPROGRAMS,. containing, first-. memory block, micro-instruction register, · first and second result triggers, 'control trigger, first, second, third and fourth AND elements, first / second and second OR elements, delay element and block of AND elements, and the output of the first AND element is connected with the read input of the first block of memory, the output of which is connected to the input of the micro-command register, the outputs of the microoperation field and the address' field of the micro-command register are connected to the inputs of the first OR element, the output of the first delay element and the zero output of the control trigger are connected Similarly: with the first and second inputs of the second AND element, the unit outputs of the first and second triggers of the result are connected to the first inputs of the third and four. addition of elements And, accordingly, the zero outputs of the first and second; result triggers are connected to the second inputs of the fourth and third elements AND, respectively, ... (the outputs of which are connected to the first and second inputs of the second element, OR, respectively, differentiating it with the fact that, in order to increase the reliability of control a start trigger, a one-shot, '. counter, second and third memory blocks, a switch, fifth, sixth and seventh AND elements, second and third. -:. delay elements are introduced into it, moreover, the device’s clock pulses input and a single trigger output start-ups are connected, respectively, with the first and the second inputs of the fifth element And, the output of which is connected to the · first inputs per-. . of the sixth and sixth elements и and through the first второй second, elements, delays with the counter input of the counter, the counter overflow output is connected to .. . with the counting input of the control trigger, · are the information outputs of the counter connected to the address inputs of the second block β memory, the first information? b. <the inputs of the switch and the first inputs of the block of AND elements, the outputs of which are connected to the information 'inputs of the first memory block, the single output of the control trigger is connected to the first control' / input of the commute. of the torus .and the second input of the sixth AND element, the output of which is connected to the read inputs of the second and third memory blocks and to the synchronization inputs of the result triggers and through. The third delay element with the third inputs of the third and fourth elements AND, the zero output of the trigger control is connected to the second inputs. <block of AND elements, the second input of the first AND element, the second control (The input of the switch and through the one-shot - with the third input of the second EL element *, the output of the address field of the micro-command register is connected to the second information input of the switch, the output of which is connected to the address input of the third block memory, the output of the second element AND is connected to the first input of the seventh element and to the recording inputs of the second and third memory blocks, the outputs of which are connected respectively to the Ό-inputs% 1OE4O42 of the first and second triggers of the result, the output of the first OR element is connected to the information input of the second memory Spock and the second input of the seventh element And, the output of which is connected to the information input of the third memory block, the output of the second element OR is connected to the zero input of the start trigger, the single input of which is the start input of the device, the outputs of the third and fourth elements AND are the first and second outputs of the device error, respectively.