SU1020961A1 - Freqeuncy multiplier - Google Patents

Abstract

MULTIPLIENT OF FREQUENCY, which contains the most common sharpener of the codes, and the first digital compo about tl and ch and y with and. that, in order to increase the precision of the repression of the multiplication factor, the serially connected shaper was introduced between the output of the narrow pulse generator and the input of the hybrid voltage generator. reference rectangular pulses, control key and low pass filter, between the driver output. The sawtooth voltage and the second input of the comparator are connected in series the normalizing driver and the second pythro-analog converter, the second inputs of which are connected to the corresponding key outputs and the input of the reference signal of the first 9 amp converter and the amp input to the output of the input source KJU reference signal, and the input of the zero pho |: o setting of the sawtooth voltage is connected to the output of the shape of the bodies of narrow pulses.

Description

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 U The invention relates to radio engineering and can be used to generate signals with a multiplication of the clock frequency, in particular, frequency sensors, as well as a synchronizing device in unfiltered spectrum analyzers, etc. A frequency multiplier is known, which is a serially connected shaper of a narrow impulse counter of pulses, a first digital-in-step converter and a comparator whose output is connected with the information input of a pulse counter, as well as a register of the multiplication coefficient code C 13 of the spherical voltage C 13 The accuracy of maintaining the multiplication factor is not high enough. The purpose of the invention is to improve the accuracy of maintaining the multiplication factor. This goal is achieved by having a frequency multiplier containing serially connected narrow pulse generator, pulse meter, first digital-to-analog converter and a comparator, the output of which is connected to the information input of the pulse counter, as well as the multiplication coefficient code register and a cone-shaped voltage former, between the output of the narrow pulse former and the input of the sawtooth former, are introduced after Consequently, a standard rectangular pulse driver, a control key and a lower filter, between the saw driver voltage output and the second input of the comparator, sequentially connected normalizing amplifier and the second digital-to-analog converter, the second inputs of which are connected to the corresponding outputs of the smart coefficient code register, the second input of the controlled key and the input of the reference signal of the first digital-to-analog converter are connected to the output of the input source Single reference signal, a set input zero shaper sawtooth voltage is coupled to the output of the narrow pulses. The drawing shows a structural electrical frequency multiplier circuit. The frequency multiplier contains shaper 1 narrow. 1pulses, 2 standard rectangular pulses, controlled key 3, low pass filter (LPF) 4, sawtooth voltage driver 5, normalizing amplifier 6, second digital-to-analog converter (D / A) 7, comparator 8, register 9 of the multiplication coefficient code, the source 10 of the reference signal, the first DAC 11, the counter 12 pulses. The frequency multiplier works as follows. The input signal with a frequency f y enters the shaper 1 narrow pulses, which forms three sequences of high borehole pulses with a frequency of the input signal. The pulses of the first sequence start the shaper 2 reference rectangular pulses, which gives the rectangular pulses of the reference D10STi to and the frequency. At the same time, the following should be observed: g- At the same time, with the start, the form 2 is set to the zero state of the counter 12 and the shaper 5 of the saw voltage, can be made as an integrator. The output pulses of the imaging unit 2 are controllers of the controlled key 3, the second input of which receives the reference stabilized voltage with the level of OOP ° T of the source 10. As a result, pulses of amplitude O on and frequency E are removed from the output of the controlled key 3. These pulses are averaged by the low-pass filter 4, and a constant voltage is generated at its output, the level of which is U (j) Hvt - Uon 0 This voltage is fed to the driver 5 (integrator), from which the linearly increasing voltage is removed (1 (x J. W -, where f, the time of the integrator, At the end of the input signal period, the driver 5 (the integrator) is zeroed out, while the voltage on it reaches its maximum value 1, (-iryiOXMHT WHT l - Tc

Further, the saw-tooth voltage c, the output of the former 5 is fed to the normalizing amplify 6 with the output ratio TOMTJ / tjjC of which the signal is removed,

Ov, tW-Uon " The output from the output of the normalizing & amplifier 6 is the reference of the second D / A converter 7. It has on its output. with signal

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where H is the multiplication factor, the code of which is entered in register 9 NjnQx the maximum number that can be written in register 9.

The output of the second DAC 7 is fed to the second input of the comparator 8, the input of which receives the output of the first DAC 11, At the initial moment (i.e., when the counter 12 is turned off and the driver 5), the voltage at both / inputs of the comparator 8 is zero.

When this happens, the comparator 8 is triggered, a pulse appears at its output, which is the output for the frequency multiplier, which is recorded in the counter 12, and the contents of the counter 12 are incremented by one. As a result, the voltage at the first input of the comparator becomes greater than at the second, and it returns to the original voltage. The sawtooth voltage continues to increase. When the potential at the second input of the comparator 8 again reaches the first input level, the comparator 8u is again triggered at the output of the multiplier

frequency appears another imp. The described process repeats before the arrival of the ocular pulse from shaper 1, which zeroes the chick 12 and shaper 5, after which the cycle repeats. The frequency of the output pulses of the comparator 8 is equal to .. The elementary increment of the output voltage of the first DAC 11 with the change of the input code received from the counting of 12 pulses by one unit in the least significant bit

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Where is the maximal number, kstfoe can & 1 is recorded in the counter 12.

.In the instant of operation of the comparator 8, the relation

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and therefore

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From here you can find the weekend period. frequency multiplier pulses

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 the proposed frequency multiplier, the accuracy of maintaining the multiplication factor is greatly increased, its dependence on the constant time of the sawtooth source is absent, as a result of which the speed is increased.

Claims (1)

A FREQUENCY MULTIPLIER containing consecutively narrowed pulse shaper, a pulse counter, a first digital-to-analog converter and a comparator, the output of which is connected to the information one, the pulse counter input, as well as the code register of the multiplication coefficients and the sawtooth shaper, with the fact that, in order to increase the accuracy of maintaining the multiplication coefficient, between the output of the narrow pulse shaper and the input of the sawtooth voltage shaper are connected in series data shaper. reference rectangular pulses, a controlled key and a filter of the lower chamber, between the output of the shaper. a sawtooth voltage and a second input of the comparator introduced a series-connected normalizing amplifier and a second digital-to-analog converter, the second inputs of which are connected to the corresponding outputs of the key and the input of the reference signal - the first digital-to-analog converter is connected to the output of the input source of the reference signal, and the zero input of the sawtooth generator is connected to the output of the sawtooth narrow pulse shaper. 1960201 1 1020961 2