SU1252928A1 - Level holder - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for measuring pulse signals. The purpose of the invention is to blaze the measurement accuracy. This is achieved by reducing the impact of impulse noise. For this, a second diode 18, a capacitor 17, an AND delay element and resistors 12, 13, 15, 19 and 22 are additionally introduced into the device. In addition, the device contains a repeater I, an input bus 2, resistors 3, 6 and 7, an inverting integrator 4 A chain 8 consisting of a resistor 9 and a diode 10, an operational amplifier 11, made on the operational amplifier 5. The device can also be used in amplifier-conversion channels of X-ray spectrometers, in which the amplitude and wellness of the pulse signals vary randomly. 2 Il. / 3 "i (L

Description

The invention relates to a pulse technique and can be used in devices for measuring pulse signals, in particular in devices in which the amplitude and duty cycle of pulse signals vary randomly.

The purpose of the invention is to increase accuracy by reducing the effect of impulse noise.

FIG. 1 is a schematic diagram of a level lock; Fig 2 shows graphs explaining the operation of the level lock.

The latch contains a repeater I, the input of which is connected to the input bus 2 through the first resistor 3, the inverting integrator 4, performed on the operational amplifier 5, the output of which is connected to the first output of the second resistor 6, and the input is connected to the first output of the third resistor 7 via a chain 8 consisting of four fourth resistor 9 and the first diode 10 connected in parallel, an operational amplifier P, the non-inverting input of which is connected to the zero potential bus through a fifth resistor 12, and the inverting input through a sixth cut a stop 13 with an output of an operational accelerator 1 and an output bus 14, directly with the second output of the second resistor 6, through the seventh resistor 5 connected in series, the delay element 16 and the capacitor I7 from the output of the repeater 1, whose input is connected to the second output of the third resistor 7, in parallel A second diode 18 is connected, through the eighth resistor 19 to the first voltage source 20, and the input of the inverting integrator .4 is connected to the second voltage source 21 via the ninth resistor 22.

The device works as follows.

A repeater 1, a capacitor 17, a delay element 16, a seventh resistor 15 form a forward channel for operating pulses. Resistor 7, billowed diode 18, chain 8, inverting integrator 4, resistor 6 form a parallel channel of operating pulses ..

FIG. 2 the real time t is plotted on the abscissa, the voltage U is plotted on the ordinate.

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pulses corresponding to a given point in time. The graphs show the relative position of the pulses produced at different points in the circuit and their shape. For definiteness, the passage of two positive polarity pulses is shown. Curve Q shows pulses at the input, curve S - pulses at the output of delay element 16 delayed by time t, curve 6 - voltage at the output of inverting integrator 4 delayed by time t, curve - output pulses fixed at and “. At the input are working pulses (Fig. 2a), random in amplitude and duty cycle, which pass through the forward channel. The passage through the capacitor 17 charges it for the duration of the operating pulse with a constant time of 7. In the time intervals between pulses, the capacitor 17 is discharged with a constant time Tp, forming a quasi-triangular charge-discharge pulses U (t), besides, it keeps some slowly varying voltage AND, the value of which is proportional to the frequency passing pulses (fig. 2b) As a result, the working impulse is superimposed on the quasi-triangular charge-discharge pulses U (t) and the voltage varying voltage U, due to the random nature of the process, which leads to a distortion of the pulse shape and to a non-fixed level .

For continuous and synchronous subtraction of quasi-triangular charge-discharge pulses U {t) and a slowly varying voltage U from the signal (Fig. 2b), a parallel channel is used, generating in anti-phase voltage, equal in shape and value

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17 (FIG. 2c), which is continuously generated from the voltage of the forward channel and restores the level

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the voltage U (t) I.I. on capacitor

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the shape and amplitude of the worker imny. ibca (Fig. 2d), the delay at time tj occurring in the parallel channel, mainly due to the integrator circuit, is compensated in the forward channel by delay element 16 with delay time t. The working pulses (Fig. 2a) are fed to the input of the inverting integrator 4, where they are transformed into an output voltage having a quasi-triangular shape that coincides in magnitude and shape in time with the same quasi-triangular charge-discharge pulses U (t) condenser 17 (fig. 2c).

In this case, the constant charge time t is determined by selecting the value of resistor 9, and the constant time value of the discharge t p is selected by selecting the value of resistor 7, the independence of the installation and tp is provided by the first 0 and second 18 diodes shunting the resistor 9 and resistor 7, respectively.

Thus, in a parallel channel, quasi-triangular charge-discharge pulses U (t) are formed. In addition, the inverting integrator 4 plays the role of an intensimeter and, depending on the pulse frequency, forms a slowly varying voltage U at its output (Fig. 2c), while the output voltage of the voltage source 21 sets the constant component slowly. variable voltage U.

As a result, a voltage arises at the output of the parallel channel, which has the form of a voltage across the capacitor 17 U (t) and finds it with antiphase (Fig. 2b, c). The time shift t ,, arising mainly from the inverting integrator 4, is compensated by the delay element 16 (Fig. 26).

By selecting the mass-stabilizing resistances of the resistors 6 and 15 from the voltage of the direct channel (Fig. 26), the voltage of the parallel channel (Fig. 2c), i.e. in fact, direct and inverted voltages are stored. As a result, the pulse shape is restored on the output bus 14 and the level is fixed. Veli

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The fixation level of the level U is set at the output of the voltage source 20.

Thus, the proposed level lock smoothly and continuously adjusts the level.

Claims (1)

Invention Formula A level lock containing a repeater, the input of which is connected to the input bus through the first resistor, an inverting integrator, is connected to the operational amplifier, the output of which is connected to the first output of the second resistor, and the input is connected to the first output of the third resistor through a chain consisting of connected in parallel the fourth resistor and the first diode, characterized in that, in order to improve accuracy by reducing the effect of impulse noise, a second diode, a capacitor, a delay element, fifth, six are introduced into it oh, seventh, eighth and ninth resistors and operational amplifier, the non-inverting input of which is connected to the zero potential bus via the fifth resistor, and the inverting input through the sixth resistor to the output of the operational amplifier and output bus directly to the second output of the second resistor, sequentially connected the seventh resistor, the delay element and the capacitor - with the output of the repeater, the input of which is connected to the second output of the third resistor, the parallel of which is connected to the second diode, through the eighth cut the stop is with the first voltage source, and the input of the inverting integrator is connected to the second voltage source; nor through the ninth resistor. .Z