SU1005063A2 - Electronic device checking system - Google Patents

Description

(54) SYSTEM FOR ELECTRONIC DEVICE CONTROL

one -

The invention relates to computing technology and can be used in the systems of automatic control of integrated circuits, as well as blocks and devices of discrete action during their production and operation.

According to the main author. St. 696464 known system for controlling electronic devices, containing digital. computer, counter, comparison unit, connected by the first and second inputs to the first input of the system and to the output of the reference signals of the digital computer, the output of the test signals of which is connected to the output of the system, the interrupt input to the output of the shift register, the fault output of the fault the counter, the stop input - with the second output of the counter and the first input of the clock generator, and the start output - with the input of the clock generator, the output of which is connected to the input of the pulse distributor, the first output meters connected to the input of the counter and the first input of the shift register, the second output to the third input, the comparison unit, and the third output to the second

the input of the shift register, the third input of which is connected to the output of the comparison unit

The lack of a system lies in its poor performance.

The aim of the invention is to improve system performance.

The goal is achieved by introducing a null 10 decoder and an OR element, the zero decoder input is connected to the second output of the shift register, and the output is connected to the first input of the OR element, the second input and output of which are connected respectively to the second output of the counter and the first input clock generator.

The drawing shows structures20 on the system diagram.

The system consists of a digital computer (DVM) 1, a shift register 2, a comparison block 3, a counter 4, a clock generator 5,

25 distributor b pulses, output tires 7 test signals, bus 8 interrupts, bus 9 fault addresses, tires 10 reference signals, 11 start, bus 12 stop, de 30 encoder 13 zero and the element OR 14

System1 works as follows.

At each step of the test sequence, digital computer 1 reads the next test code set consisting of ones and zeros from the memory and issues this code to the monitored object, then sends bus 10 digital computers 1 to the block 3 with the reference code corresponding to the response signals of the monitored object. Upon completion of the transient processes in the controlled object, the digital computer 1, via bus 11, starts the clock generator 5, which begins to generate a sequence of clock pulses, after which the digital computer 1 is released from the control of this object and can be used to control other electronic devices

Clock pulses arrive at the distributor b. The first clock pulse goes to the control (third) input of the comparison unit 3, the second input of which is connected to the outputs of the monitored object connected to the system input. The first clock pulse allows the comparison of the signals of the object being monitored with the reference. As a result of the comparison, at block 3, a code is generated containing units in those bits where the comparison did not occur. On the second clock pulse, block code 3 is rewritten to shift register 2.

If the decoder 13 generates a signal indicating that there are no units on the shift register 2, this signal through the OR 14 element is fed through bus 12 to the input of CSH 1 and to the input of the clock generator 5, blocking the generation of clock pulses.

If the shift register 2 contains a code containing the units, all the post-clock clocks are sent to the shift register 2 and counter 4, where each clock pulse is shifted by one bit, and the unit is added to counter 4. If there is a shift at the output of the shift register 2, a signal of a logical unit appears, indicating that the signal of this

the monitored object with the reference, then the interrupt signal is received via bus 8 interrupts in the digital computer 1. The contents of counter 4 at this moment indicate the number of the bit in which.

incomparability occurred.

Having received the rerouting signal, digital computer 1 receives and records the contents of counter 4 via bus 9 of the fault address, and then passes

to control other devices. When the next mismatch occurs, the process repeats.

If there are no units in the remaining bits after the next mismatch, the diffuser 13 generates a signal indicating that there are no units on the shift register 2, which through the OR 14 element comes through the bus 12 to the input of the digital computer 1 and

to the input of the clock generator 5, block the production of clock pulses.

On the test end signal, the digital computer 1 either issues the next test code, or decrypts the faults.

Thus, the system eliminates the overhead of consistently viewing all the bits of the shift register, which will increase the performance of the system.

Claims (1)

Invention Formula System for controlling electronic devices St. No. 696464, in order to improve the performance of the system, the zero decoder and the OR element are entered into it, and the zero decoder input is connected to the second output of the shift register, and the output to the first input of the OR element, the second input and output of which respectively connected to the second output 5 counter and the first input of the clock generator. . Sources of information taken into account in the examination 1. USSR author's certificate 0 696464, cl. G Q6 F 11/26, 1977 (prototype).