SU1002991A1 - Device for checking radioelectronic circuit threshold levels - Google Patents

Description

J The invention relates to measuring instrumentation and can not be used in the construction of automated testing equipment for measuring parameters of radio electronic circuits, for example, microcircuits, h®iKpoc6opoK. The threshold voltage meter of logic circuits, the contents of a clock generator, a selector, a decoder counter, a trigger, a source for linearly varying the system voltage, a comparator, a reset generator, and a load line 1 is known.} The disadvantage of this device is the low accuracy of the control due to the fact that The levels are measured in a static, rather than dingy mode. The closest technical solution to the invention is the device dTBO for monitoring threshold levels of radio electronic circuits comprising a generator, a sawtooth voltage, switches, a converter and a high frequency (HF) signal generator, 2. The known device allows automatic measurement of threshold voltages of potential logic circuits since the sum of the low-frequency pi signal and the RF signal is applied to the circuit under test. In this case, the verifiable circuit is actually brought to the threshold by a saw-tooth voltage, i.e. ; in this case, the sensitivity (threshold, response) of the circuit is measured by a low-frequency signal, the B4-cHiv mally | cash provides only a minor contribution to the total amount of input voltages; and serves only to more accurately capture the output level at which the input threshold level is determined. Such a measurement technique is only feasible if the threshold levels or the sensitivity of the circuit are determined by the direct current or by the low-frequency (quasi-constant) signal. However, for high-speed impulse circuits, it is of interest to consider the sensitivity of a high-frequency signal (a pulse of short duration), which can significantly (by an order of magnitude and more) differ from the sensitivity on a low-frequency signal. In the known device, where, as mentioned, a low hour sawtooth voltage acts on the input of the circuit under test, the sensitivity of the circuit under test to the low frequency signal or DC is measured, which determines the low reliability of the result of the test. In addition, high-frequency threshold circuits very often contain a separator capacitor in the input signal circuit, and the higher the speed of the circuit, the lower the capacitance of this capacitor. In this case, the low-frequency sawtooth signal either does not pass through this capacitor at all, or transmits with large distortions, which does not allow to measure the sensitivity with the required accuracy and reduces the reliability of the control result. In addition, low interference resistance is low. The visibility reduces the reliability of the control, since in the process of measurement the actuation of the fixation circuit occurs once at the moment when the sum of the sawtooth voltage and the RF signal of the controlled threshold level is reached. Therefore, the effect of a single noise of sufficient magnitude at any time of changing the sawtooth voltage can lead to the triggering of the latching circuit and, consequently, to registration. The purpose of the invention is to increase the reliability of control results. The goal is achieved by the fact that in a device for monitoring threshold levels of electronic circuits, comprising a rising voltage generator, a first generator, a pulse, a meter connected by a first input to an input of a controlled electronic circuit, a discriminato connected by a first input to an output of a controlled electronic circuit, the second input an input unit, a control unit connected by the first output to the second input of the meter, an element I, a drive and a gating unit are connected, connected by the first input to the output a secondary voltage generator, a second input — with the output of the element I, connected inlet to the output of the first generator and pulses, a second input — with the second output of the control unit, the third output of which is connected to the first input of the accumulator and the first input of the voltage generator , the fourth input - with the second input of the rising voltage generator, connected by the third input to the drive output, connected by the second input to the discriminator output, and the fact that the rising voltage generator is the second impulse generator The key, the key, the counter and the digital-analogue converter connected by the output to the generator output input - With the output of a counter connected by the first input to the first input of the generator, the second input to the output of a key connected by the first INPUT to the second input of the generator, the second input to the second output pulse generator, the third input with the third input of the generator, and the fact that the gating unit contains the first, second and third resistors and the first and second transistors, and the first input of the gating unit is connected via the first ezistor with the base of the first transistor, an emitter connected through a second resistor to a power bus directly to the output of the gating and the collector of the second transistor, an emitter connected to the bus earth and the collector of the first transistor via the third base rezistors second input gating unit. FIG. 1 shows the block diagram of the proposed device; in fig. 2 diagrams, as per the operation of the proposed device j in FIG. 3 is an electrical block gating circuit. The device contains a control unit 1, a rising voltage generator 2, a second pulse generator 3, a key 4, a counter 5, a D / A converter D / A converter 6), a first pulse generator 7, an AND unit 8, a gating unit 9, a test circuit 10, a meter 11, the discriminator 12, the drive 13. The device operates as follows. In the initial state, from the control unit 1, the potentials of the cascades (oscillograms in FIGS. 2 a, b) enter the inputs of the element 8 and the key 4, as a result of which the pulses of the generators 3 and 7 do not pass to the outputs of the key 4 and element 8. At the moment of starting the measurement, determined / for example, by pressing the Start button in the control unit 1, from the control unit 1 to the input of the key 4 arrives & allow enable pulse Up (Fig. 26), the duration of which is equal to the duration of the measurement cycle . Simultaneously; At the input of counter 5 and input of accumulator 13, a reset pulse (oscillogram in Fig. 2c), setting the counter 5, and hence the DAC 6 to the zero state and discharging the accumulative capacity in the accumulator 13 from voltage u to zero. As a result, the inputs of the key 4 (which can be performed, for example, in the form of a three-input element AND –NON O) receive the voltage Up-uU ciO (Fig. 2d), which ensures the passage of counting pulses (Fig. 26 ) from the generator 3 to the output of the key 4, i.e. at the entrance

counter 5 (voltage U in Fig. 2e).

Counter 5 starts counting these pulses, which leads to the sequential switching on of bits of the CLP 6 (starting from the youngest), with the result that a stepwise increasing voltage is formed at the output of the CLP 6 (the oscillogram in Fig. 2e) arriving at the input of the gating unit 9.

So as with the beginning of the measurement cycle, the impulse U (oscillogram on phg. 2a) arrives at the input of the And 8 element. The test pulses (UKM in Fig. 2g) from the generator 7 pass through the And 8 element, at the input of which gating pulses occur. U (waveform in figv).

Thus, at the gates of the gating unit i9, there are gating pulses U. and a stepwise impaction

FIG. Figure 3 shows a possible embodiment of an AND 8 element and a gating block on transistors 17 and 18: the base of transistor 17 is supplied with voltage from the output of the DAC 6, and test pulses from the output of element And 8 are fed to the base of transistor 18.

When a high potential transistor 18 (Fig. 3) is applied to the base, this transistor opens and shunts the output of the emitter follower on transistor 17, while the voltage on the emitter is close to zero. When the base potential of transistor 18 is applied, a low potential "O, transistor 18 is closed and does not shunt the emitter circuit of the transistor 17, while the voltage from the base of the transistor 17 passes to the repeater output. As a result, at the output of the emitter follower 17, i.e. at the output of the gating unit 9, a pulse voltage with stepwise amplitude is formed, and the pulse magnitude within each step has a constant value (the waveform in Fig. 2i). The step size is chosen less than the permissible error of sensitivity measurement.

 The duration of each step is determined by the period of the next account (1xX pulses from generator 3, and the number of test pulses within one stage is determined by the ratio of the periods of the pulse of generators 3 and 7.

The voltage from the output of the gating cascade as an inrush voltage Ug is applied to the circuit under test 10. The output voltage of this circuit varies in accordance with the form of its transfer characteristic, for example, as shown in the waveform diagram of FIG. 2K, and at a certain step, the amplitude of the high frequency pulses of the tested circuit 10 reaches the value U, at which the Triggering threshold or pulse sensitivity of the circuit Ugj is determined. This triggers the discriminator 12, to which the reference voltage U is applied, corresponding to the voltage

The pulses from the output of the discriminator 12 (CD in Fig. 2l) are fed to a drive 13 / made, for example, according to the peak detector circuit, and the storage tank is charged (the oscillogram in Fig.), From which the voltage U goes to one of the inputs key 4. When the voltage Tsc reaches a certain value U, sufficient for locking key 4, the latter closes and the flow of counting pulses from generator 3 to the input of counter 5 stops (Fig. 2e), as a result of which the voltage buildup in the DAC stops its output is set by a constant voltage equal to the voltage of the step, at which the input impulse voltage of the circuit under test Ug achieves the response threshold llSv .В

ol

As a result, until the resolution pulse Up is terminated, constant amplitude pulses will arrive at the input of the tested circuit and gx. After the resolution pulse ends, the potential of the logic zero is established at the output of element 8, resulting in the transistor 18 of block 9 of fig. 3) is permanently closed, and at the output of the cascade (collector of transistor 17) a constant voltage LL is set, the value of which is equal to the amplitude of the pulses, at which the output voltage of the tested circuit reaches the value of the outputs, i.e. U- UcJ (Fig. 2i). The voltage U is fed to the input of the DC voltage meter 11, to the start input of which a signal is supplied from the control unit 1 (pulse Uj in FIG. 2H). As a meter, you can use, for example, an electronic digital voltmeter, which, when a specified trigger signal arrives, registers the voltage U, i.e. measured value. impulse sensitivity of the tested circuit. The meter 11 can be made in the form of a DC voltage discriminator (e.g., an operational amplifier-comparator), in this case control is provided on the basis of a good-marriage principle.

Claims (2)

In the proposed device, pulses are supplied to the input of the tested circuit 10, the parameters of which (duration, frequency) are set by the generator 7 in accordance with the requirements imposed on the input pulse, the circuit itself is measured when measuring its pulse sensitivity, Ultimately, the DC voltage is equal to the required pulse sensitivity. The proposed device thus allows, as well as the known device, to measure the threshold voltages of logic circuits for any duration of the input signal, however, unlike the known device, it makes it possible to measure the pulse sensitivity of high-speed impulse circuits any short duration of the input pulses, determined by the generator 7 and the speed of the element. and 8 and the gating unit 9. As a result, the functionality of the proposed device is greatly expanded. In addition, due to the measurement of a constant voltage, instead of measuring the amplitude. short impulses, the measurement accuracy of the impulse increases significantly (Noah sensitivity. The voltage on drive 13 reaches the value U, at which the voltage rise of the DAC 6 stops, when a drive arrives at the drive some N pulses from the discriminator 12, i.e. the tested circuit of 10 N input pulses. This number N can be made by any means by appropriately choosing the constant charge time of the capacitor in the accumulator 13 and choosing the appropriate ratio of the DAC step 6, i.e. and the counting pulses of the generator 3 and the period of the test pulses of the generator 7. As a result, if a tested circuit is accidentally triggered from any single or short-term interference, the voltage on the drive will not reach the value UJ., and, therefore, the voltage of the DAC. continue to grow until it reaches a value at which steady operation of the tested circuit begins. Thus, the introduction of the storage device 13 into the proposed device significantly increases its noise immunity of the PSR compared to the known device (which ultimately also increases the measurement accuracy). Claim 1. Device for monitoring threshold levels of electronic circuits comprising a rising voltage generator, a first pulse generator, a meter connected by a first input to an input of a controlled electronic circuit, a discriminator connected by a first input to an output of a controlled electronic circuit, the second input to an input device, a control unit connected by a first output to a second input of the meter, characterized in that, in order to increase the reliability of the control, an element I, n is inserted into the device a collector and a gating unit connected by the first input to the output of the rising voltage generator, by the second input to the output of the And element connected by the first input to the output of the first pulse generator, the second input to the second output of the control unit, the third output of which is connected to the first input of the accumulator and with the first input of the voltage generator; the fourth output with the second input of the voltage generator connected with the third input with the drive output connected with the second input with the discrimination output Torah. 2. A device according to claim 1, characterized in that the voltage generator contains a second pulse generator, a key, a counter and a digital-to-analog converter connected to the output with an output of the generator, the input to the output of the counter connected to the first input of the c. the first input of the generator, the second input - with the output of a key connected by the first input with the second input of the generator, the second input - with the output of the second pulse generator, the third input - with the third input of the generator. 3. The device according to claim 1, is different in that the gating unit contains first, second 1 and third resistors and first and second transistors, the first input of the gating unit connected via the first resistor to the base of the first transistor c. a power bus, directly with the output of the gating unit and a collector of the second transistor connected by an emitter with the bus Earth. and with the collector of the first transistor, the base through the third resistor by the second input of the gating unit. Sources of information taken into account in the examination 1. Authors certificate of the USSR, № 526833, cl. G. 01 R 31/28, 1976. 2. USSR author's certificate number 266943, cl. G 01 R 31/28-, 1970 (prototype).