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SG11202005030XA - Catalyst influenced pattern transfer technology - Google Patents

Catalyst influenced pattern transfer technology

Info

Publication number
SG11202005030XA
SG11202005030XA SG11202005030XA SG11202005030XA SG11202005030XA SG 11202005030X A SG11202005030X A SG 11202005030XA SG 11202005030X A SG11202005030X A SG 11202005030XA SG 11202005030X A SG11202005030X A SG 11202005030XA SG 11202005030X A SG11202005030X A SG 11202005030XA
Authority
SG
Singapore
Prior art keywords
pattern transfer
transfer technology
catalyst influenced
influenced pattern
catalyst
Prior art date
Application number
SG11202005030XA
Inventor
Sidlgata V Sreenivasan
Akhila Mallavarapu
Shrawan Singhal
Lawrence R Dunn
Brian Gawlik
Original Assignee
Univ Texas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Texas filed Critical Univ Texas
Publication of SG11202005030XA publication Critical patent/SG11202005030XA/en

Links

Classifications

    • H10P50/642
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • H10D30/6212Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H10D30/6213Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections having rounded corners
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6757Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H10P50/242
SG11202005030XA 2017-11-28 2018-11-09 Catalyst influenced pattern transfer technology SG11202005030XA (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762591326P 2017-11-28 2017-11-28
US201862665084P 2018-05-01 2018-05-01
US201862701049P 2018-07-20 2018-07-20
US201862729361P 2018-09-10 2018-09-10
PCT/US2018/060176 WO2019108366A1 (en) 2017-11-28 2018-11-09 Catalyst influenced pattern transfer technology

Publications (1)

Publication Number Publication Date
SG11202005030XA true SG11202005030XA (en) 2020-06-29

Family

ID=66665736

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202005030XA SG11202005030XA (en) 2017-11-28 2018-11-09 Catalyst influenced pattern transfer technology

Country Status (8)

Country Link
EP (1) EP3718133A4 (en)
JP (3) JP7328220B2 (en)
KR (2) KR20250096882A (en)
CN (1) CN111670493B (en)
MY (1) MY209531A (en)
SG (1) SG11202005030XA (en)
TW (2) TW202534795A (en)
WO (1) WO2019108366A1 (en)

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EP4097754A4 (en) * 2020-01-27 2024-01-24 SMENA Catalysis AB STRUCTURING OF MULTILAYER TRANSITION METAL DICHALCOGENIDES
US11367778B2 (en) * 2020-03-31 2022-06-21 Taiwan Semiconductor Manufacturing Company Limited MOSFET device structure with air-gaps in spacer and methods for forming the same
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US11257758B2 (en) * 2020-06-24 2022-02-22 Taiwan Semiconductor Manufacturing Company Limited Backside connection structures for nanostructures and methods of forming the same
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CN116130351B (en) * 2022-11-25 2025-11-04 中国科学院声学研究所 A method for fabricating micro-silicon spherical cavities
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KR102674927B1 (en) * 2023-09-15 2024-06-14 아이티팜 주식회사 Apparatus and method for detecting abnormalities in the semiconductor manufacturing process through sem image analysis using ai image processing technology
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Also Published As

Publication number Publication date
JP2025098124A (en) 2025-07-01
WO2019108366A1 (en) 2019-06-06
KR20250096882A (en) 2025-06-27
CN111670493A (en) 2020-09-15
KR102824535B1 (en) 2025-06-23
JP2023145718A (en) 2023-10-11
TWI884126B (en) 2025-05-21
TW202534795A (en) 2025-09-01
EP3718133A1 (en) 2020-10-07
KR20200090237A (en) 2020-07-28
JP7655989B2 (en) 2025-04-02
JP7328220B2 (en) 2023-08-16
TW201926460A (en) 2019-07-01
CN111670493B (en) 2024-06-28
MY209531A (en) 2025-07-17
JP2021504961A (en) 2021-02-15
EP3718133A4 (en) 2021-11-24

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